Taiwan Semiconductor Manufacturing Comp. Ltd.

Li-Hsien Huang

An-Jhih Su

Hsien-Wei Chen

Der-Chyang Yeh

Chen-Hua Douglas Yu

Wei-Yu Chen

Ming-Shih Yeh

Chi-Hsi Wu

Hua-Wei Tseng

Tien-Chung Yang

Yueh-Ting Lin

Yao-Chun Chuang

Ming Shih Yeh

Shin-Puu Jeng

Wen-Chih Chiou

Wei-Cheng Wu

Ying-Ju Chen

Tsang-Jiuh Wu

Cheng-Hung Chang

Chia-Lin Yu

Jun He

Ebin Liao

Chun Hua Chang

Hsiang-Yi Wang

Chiang Lin

Darryl Kuo

Po-Hao Tsai

Shuo-Mao Chen

Tsung-Shu Lin

Chin-Chuan Chang

Ching-Wen Hsiao

Ta-Wei Liu

Wei-yu Chen

Yu-Hsiang Hu

Wan-Yu Lee

Ting-Ting Kuo

Yinlung Lu

Lin-Chih Huang

Shao-Yun Chen

Kuan-Chung Lu

Chung-Shi Liu

Hung-Jui Kuo

Guan-Yu Chen

Ching-Pin Lin

Chien-Yu Li

Chi-Jung Lee

SyuFong Li

Chien-Li Kuo

Chien-Hung Chen

Ming-Chih Yew

Li-Hui Cheng

Chih-Lin Wang

Chun-Jen Chen

Yi-Jen Lai

Chien-Chen Li

Yan-Fu Lin

Yung-Sheng Liu

Chin-Hsien Chen

Jo-Mei Wang

Hsueh-Lung Cheng

Shih-Kang Tien

Ming-Feng Wu

Cheng-Pu Chiu

Ta-Hsuan Lin

Yung-Shou Cheng

A laser grooving operation is performed to form a plurality of grooves in a semiconductor die prior to attaching the semiconductor die to a semiconductor device package substrate. In addition to forming a first groove through which blade sawing is to be performed to separate the semiconductor die from other semiconductor dies, a second groove may be formed between the first groove and a seal ring of the semiconductor die. The second groove is configured to contain any potential delamination that might otherwise propagate to an active region of the semiconductor die. Accordingly, the second groove and the associated laser grooving operation described herein may reduce the likelihood of delamination that might otherwise be caused by swelling and/or expansion in a molding compound formed around the semiconductor die after the semiconductor die is attached to the semiconductor device package substrate.

Semiconductor device package and methods of formation

The present disclosure provides methods and structures to prevent cracks in redistribution layers. A redistribution structure according to the present disclosure includes a first polymer layer disposed over a silicon substrate, a first contact via disposed in the first polymer layer, a second polymer layer disposed over the first contact via, a first redistribution layer including a first conductive pad disposed on the second polymer layer and a second contact via extending through the second polymer layer to physical contact the first contact via, a third polymer layer disposed over the first redistribution layer, a second redistribution layer including a second conductive pad disposed on the third polymer layer and a plurality of third contact vias extending through the third polymer layer to physically contact the first conductive pad. The first conductive pad has at least one opening and the second conductive pad has at least one opening.

Reduction of cracks in redistribution structure

A semiconductor package structure is provided. The semiconductor package structure includes: a die having a frontside and a backside; a first redistribution layer (RDL) structure disposed on the backside of the die; a second RDL structure disposed on and electrically connected to the frontside of the die; a through integrated fan-out via (TIV) disposed lateral to the die and extending to electrically connect the first and the second RDL structures; a molding compound disposed between the first and second RDL structures; an enhancement layer disposed on the second RDL structure; a plurality of pre-solder bumps; and a plurality of solder balls disposed on and electrically connected to the second RDL structure. The enhancement layer includes a plurality of cascaded openings electrically connected to the first RDL structure. Each of the pre-solder bumps is disposed in one of the cascaded openings.

Fan-out package structures with cascaded openings in enhancement layer

Device, package structure and method of forming the same are disclosed. The device includes a die encapsulated by an encapsulant, a conductive structure aside the die, and a dielectric layer overlying the conductive structure. The conductive structure includes a through via in the encapsulant, a redistribution line layer overlying the through via, and a seed layer overlying the redistribution line layer. The dielectric layer includes an opening, wherein the opening exposes a surface of the conductive structure, the opening has a scallop sidewall, and an included angle between a bottom surface of the dielectric layer and a sidewall of the opening is larger than about 60 degrees.

Package structure and manufacturing method thereof

A semiconductor package includes a semiconductor die including an active surface and an electrical terminal on the active surface, and a redistribution circuitry disposed on the active surface of the semiconductor die and connected to the electrical terminal. A top surface of the redistribution circuitry includes a planar portion and a concave portion connected to the planar portion, the concave portion is directly over the electrical terminal, and a minimum distance measured from a lowest point of the concave portion to a virtual plane where the planar portion is located is equal to or smaller than 0.5 μm.

Semiconductor package and method of manufacturing the same

A method of packaging a semiconductor includes: positioning first and second semiconductor dies by one another on a carrier substrate, wherein first and second zones zone are defined with respect to the first die and third and fourth zones are defined with respect to the second die; forming first vias in the first zone, the first vias having a first size; forming second vias in the second zone, the second vias having a second size different from the first; forming third vias in the third zone, the third vias having a third size; forming fourth vias in the fourth zone, the fourth vias having a fourth size different from the third; and electrically connecting the first and second dies with an interconnection die such that electrical signals are exchangeable therebetween.

Integrated fan-out platform and manufacturing method for semiconductor devices

A chip package and a method of fabricating the same are disclosed. The chip package includes a substrate with a first region, a second region surrounding the first region, and a third region surrounding the second region, a device layer disposed on the substrate, a via layer disposed on the device layer, an interconnect structure disposed on the via layer, and a stress buffer layer with tapered side profiles disposed on the interconnect structure. First and second portions of the via layer above the first and second regions include first and second set of vias. First, second, and third portions of the interconnect structure above the first, second, and third regions include conductive lines connected to the devices, a first set of dummy metal lines connected to the second set of vias, and a second set of dummy metal lines.

Delamination control of dielectric layers of integrated circuit chips

In an embodiment, a device includes: an integrated circuit die; a first dielectric layer over the integrated circuit die; a first metallization pattern extending through the first dielectric layer to electrically connect to the integrated circuit die; a second dielectric layer over the first metallization pattern; an under bump metallurgy extending through the second dielectric layer; a third dielectric layer over the second dielectric layer and portions of the under bump metallurgy; a conductive ring sealing an interface of the third dielectric layer and the under bump metallurgy; and a conductive connector extending through the center of the conductive ring, the conductive connector electrically connected to the under bump metallurgy.

Semiconductor packages

In an embodiment, a method includes attaching a first package component to a first carrier, the first package component comprising: an aluminum pad disposed adjacent to a substrate; a sacrificial pad disposed adjacent to the substrate, the sacrificial pad comprising a major surface opposite the substrate, a protrusion of the sacrificial pad extending from the major surface; and a dielectric bond layer disposed around the aluminum pad and the sacrificial pad; attaching a second carrier to the first package component and the first carrier, the first package component being interposed between the first carrier and the second carrier; removing the first carrier; planarizing the dielectric bond layer to comprise a top surface being coplanar with the protrusion; and etching a portion of the protrusion.

Semiconductor package and method of forming same

A method includes attaching a first-level device die to a dummy die, encapsulating the first-level device die in a first encapsulating material, forming through-vias over and electrically coupled to the first-level device die, attaching a second-level device die over the first-level device die, and encapsulating the through-vias and the second-level device die in a second encapsulating material. Redistribution lines are formed over and electrically coupled to the through-vias and the second-level device die. The dummy die, the first-level device die, the first encapsulating material, the second-level device die, and the second encapsulating material form parts of a composite wafer.

Devices employing thermal and mechanical enhanced layers and methods of forming same

Embodiments provide metal features which dissipate heat generated from a laser drilling process for exposing dummy pads through a dielectric layer. Because the dummy pads are coupled to the metal features, the metal features act as a heat dissipation feature to pull heat from the dummy pad. As a result, reduction in heat is achieved at the dummy pad during the laser drilling process.

Heat dissipating features for laser drilling process

A method includes forming a first semiconductor device, wherein the first semiconductor device includes a top surface and a bottom surface, and wherein the first semiconductor device includes a metal layer having an exposed first surface. The method also includes forming a Electromagnetic Interference (EMI) layer over the top surface and sidewalls of the first semiconductor device, wherein the EMI layer electrically contacts the exposed first surface of the metal layer. The method also includes forming a molding compound over the EMI layer.

Semiconductor device with electromagnetic interference film and method of manufacture

Stacked semiconductor devices and methods of forming the same are provided. Contact pads are formed on a die. A passivation layer is blanket deposited over the contact pads. The passivation layer is subsequently patterned to form first openings, the first openings exposing the contact pads. A buffer layer is blanket deposited over the passivation layer and the contact pads. The buffer layer is subsequently patterned to form second openings, the second opening exposing a first set of the contact pads. First conductive pillars are formed in the second openings. Conductive lines are formed over the buffer layer simultaneously with the first conductive pillars, ends of the conductive lines terminating with the first conductive pillars. An external connector structure is formed over the first conductive pillars and the conductive lines, the first conductive pillars electrically coupling the contact pads to the external connector structure.

Stacked semiconductor devices and methods of forming same

A package structure including IPD and method of forming the same are provided. The package structure includes a die, an encapsulant laterally encapsulating the die, a first RDL structure disposed on the encapsulant and the die, an IPD disposed on the first RDL structure and an underfill layer. The IPD includes a substrate, a first connector on a first side of the substrate and electrically connected to the first RDL structure, a guard structure on a second side of the substrate opposite to the first side and laterally surrounding a connector region, and a second connector disposed within the connector region and electrically connected to a conductive via embedded in the substrate. The underfill layer is disposed to at least fill a space between the first side of the IPD and the first RDL structure. The underfill layer is separated from the connector region by the guard structure.

Package structure including IPD and method of forming the same

A chip package structure is provided. The chip package structure includes a redistribution structure and a first chip structure over the redistribution structure. The chip package structure also includes a first solder bump between the redistribution structure and the first chip structure and a first molding layer surrounding the first chip structure. The chip package structure further includes a second chip structure over the first chip structure and a second molding layer surrounding the second chip structure. In addition, the chip package structure includes a third molding layer surrounding the first molding layer, the second molding layer, and the first solder bump. A portion of the third molding layer is between the first molding layer and the redistribution structure.

Chip package structure with bump

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Zhubei, Taiwan

Li-Hsien Huang