Xerox Corporation

Li-Fung Cheung

Uoc H Nguyen

Sam S Su

Simon M Law

Mehrdad Zomorrodi

George Apostol, Jr

Daniel H Greene

Fred F Hubble, Iii

George L Eldridge

James P Martin

Farzin Blurfrushan

San A Phong

Jean-Swey Kao

Robert E Crumrine

Randolph H Bullock

Tom Henning

Peter P White

A method of improving the compression ratio of image data in the form of foreground data printed over background data by arranging both kinds of data pixels into 8 by 8 pixel blocks. All blocks that do not contain at least one pixel to be printed are deleted before compression. The deleted blocks will be entirely background pixels that will be overlaid by foreground pixels, or entirely foreground pixels that will not be printed because they are located outside of foreground masks.

Segmenting image data into blocks and deleting some prior to compression

A circuit for implementing a substitutional compressor. Comparators compare a current input pixel against a large number of previous pixels, the 'history', stored in a series of shift registers. Each register and associated comparator constitutes a cell. If one or more matches are found the history data is shifted one pixel, the non-matching cells are disabled, and the next input pixel is compared against the contents of the same cells that had the previous matches. The matching is terminated when the longest series of matching pixels is found. The output code is then the length of the matching series of pixels, and the displacement of the first input pixel from the first matching pixel. An encoder generates an initialize signal that resets all of the disabled cells on the same clock cycle on which the output code word is generated. To make the circuit more compact, the cells can be arranged into a square format with one output line for each row and column from the cells to the encoder.

String-match array for substitutional compression

A system for changing the source and destination devices of data transfers under software control. Default data transfers are made from numbered source devices to the same-numbered destination devices, the data requests being routed through multiplexers which pair, for example, source 1 with destination 1, source 2 with destination 2, etc. The multiplexer control signals originate in a register which is originally loaded with default control bits. However, in real time, the bits within the control register can be re-loaded to provide outputs other than the default values. Then, the data from a source can be directed to any one of the destination devices.

Circuit for interfacing data busses

A circuit for enabling data transfer between one data bus connected to a number of devices, such as accelerator cards, and a second data bus, such as one found in a computer. The two data busses are connected by a number of FIFO buffers, and an arbitrator selects a source and destination for each packet. The circuit allows the computer to freeze the data in any or all buffers so that it can be inspected and changed if necessary, but only after the entire current packet for the selected buffer or buffers has been transferred.

Circuit for freezing the data in an interface buffer

A method is described for determining readiness of devices in a digital data bus system to transfer data signals. The bus system includes a bus having a clock line for communicating a clock signal, address lines for communicating address signals, data lines for communicating data signals, and control lines for communicating control signals. The bus system also includes a plurality of devices. Each device is connected to the bus and has an address on the bus. At least one device is a source device capable of sending data signals and at least one device is a destination device capable of receiving data signals. A bus controller connects to the bus and controls the bus. The control lines include bus request lines that connect each device to the bus controller for communicating a bus request signal from a device to the bus controller. The bus request signal indicates that the device is ready to send or receive data signals. The bus controller includes matching logic that stores the identities of predetermined pairs of a source device and a destination device between which matching logic will permit the transfer of data signals. The matching logic receives the bus request signals and determines based on the bus request signals whether a particular allowed pair of source and destination devices are ready to send and receive data signals. According to the method, a source device generates a bus request signal on the bus request lines indicating whether the source device is ready to send data signals on the data lines. Next, a destination device generates a bus request signal on the bus request lines indicating whether the destination device is ready to receive data signals on the data lines. Finally, the matching logic receives the bus request signal generated by the source device and the bus request signal generated by the destination device and, provided the pair of destination and source device are a pair allowed to transfer data signals, decides based on the received bus request signals whether the pair of the destination and source devices is ready to send and receive data signals.

Method of determining devices requesting the transfer of data signals on

A new and improved decoder for decoding CCITT compressed image data. This decoder separates all the incoming codes into short codes and long codes. The short codes are sent to the short channel decoder and the long codes are sent to the long channel decoder. At each decoding cycle either the long channel decoder or the short channel decoder is active. The short channel decoder has a twin set decoder which decodes two short codes in parallel and guarantees two bits of decompressed data per decoding cycle. If the decoding of a first code generates a decompressed data of only one bit, then the decompressed data of a second code will be combined with the first decompressed data and the combination will be sent out. This process guarantees at least two bits of decompressed data per decoding cycle. The long channel decoder decodes the long intermediate codes which always generate at least four bits of decompressed data.

High speed CCITT decompressor

The present invention is concerned with a self-adjusting document sensor compensating for degradation of the sensor system. A suitable light source and a detector are provided, the output of the detector being fed into an amplifier whose gain depends upon a feedback signal. Periodically, the output of the amplifier is compared to a reference. If the output of the amplifier falls below the reference, a pulse is sent to a ripple counter whose digital output is fed back to the amplifier to change the gain of the amplifier. If the detector is an unbiased photodiode operating in the transconductance mode, the leakage currents and their subsequent effect on output with amplifier gain changes will be minimized.

Dirt insensitive optical paper path sensor

An integrated circuit chip with digital and analog circuits thereon for providing a low cost infrared reflectance densitometer for detecting relative toner density on a photoreceptive surface including several stages of calibration including photodiode detection means 208 for monitoring and controlling the light output from a light emitting diode 206, photodiode means 302 for detecting undesired scattered and reflected background light signals, further photodiode means 304 for detecting the light reflected from said photoreceptive surface as may be affected by toner deposited thereon, an automatic gain control circuit 400 for automatically adjusting the output gain of the reflectance densitometer, and sample and hold circuit means 600 for adjusting the circuit for different effects of the aging, leakage current effects, or other undesired performance characteristics of the circuit components.

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Alhambra, CA, United States of America

Li-Fung Cheung