Changxin Memory Technologies, Inc.

Li Ding

Heng-Chia Chang

Chuanqi Shi

Zhan Ying

Jun He

Jie Liu

A semiconductor structure and a method for manufacturing the semiconductor structure are provided. The semiconductor structure includes: a substrate including a first doped region; a first isolation structure located in the first doped region, a depth of the first isolation structure being greater than that of the first doped region; a first gate structure located on the surface of the substrate of the first doped region and spanning the first isolation structure, a projection width of the first gate structure on the substrate being larger than that of the first isolation structure on the substrate; and second gate structures located on the surface of the substrate and at both sides of the first gate structure.

Semiconductor structure and method for manufacturing same

Embodiments of the present disclosure provide a memory test method and a device thereof, an electronic device, and a computer-readable storage medium, which relate to the field of semiconductor device testing technologies. The method is executed by a built-in self-test circuit and includes: acquiring defect information of a first memory by testing the first memory; acquiring repair information of the first memory based on the defect information of the first memory; and storing the repair information of the first memory in a second memory.

Method for testing memory by built-in self-test storage space and related device

Embodiments of the present disclosure provide a test method and apparatus for a control chip, and an electronic device, which relate to the field of semiconductor device test technologies. The control chip includes a built-in self-test BIST circuit. The method is performed by the BIST circuit. The method includes: reading first test vectors stored in a first target memory chip; sending the first test vectors to the control chip; receiving first output information returned by the control chip in response to the first test vectors; and acquiring a first test result of the control chip based on the first output information and the first test vectors corresponding to the first output information. By means of the technical solutions provided in the embodiments of the present disclosure, so that a storage space for test vectors can be enlarged, and the test efficiency can be increased.

Test method for control chip and related device

Embodiments of the present disclosure provide a test method and apparatus for a control chip, an electronic device, relating to the field of semiconductor device test technology. The method includes: reading first test vectors stored in a first target memory chip; sending the first test vectors to the control chip; receiving first output information returned by the control chip in response to the first test vectors; and acquiring a first test result of the control chip based on the first output information and the first test vectors corresponding to the first output information. By means of the technical solutions provided in the embodiments of the present disclosure, a memory chip can be used for storing test vectors for a control chip, so that a storage space for test vectors can be enlarged, and the test efficiency can be increased.

A memory test method includes: testing a first memory to acquire defect information of the first memory; acquiring repair information of the first memory according to the defect information of the first memory; and storing the repair information of the first memory in a second memory. In the technical solutions provided in the embodiments of the present disclosure, other memories may be used to store the repair information of the currently tested memory, so that the storage space can be increased and the test efficiency can be improved.

Memory test methods and related devices

A memory test method and apparatus, an electronic device, and a computer-readable storage medium are provided. The method includes: obtaining a test instruction; generating, in response to the test instruction, a test clock signal, a to-be-tested address and to-be-tested data; determining a to-be-tested memory from memories of a storage device, the storage device including a self-test circuit; writing the to-be-tested data into a storage unit corresponding to the to-be-tested address of the to-be-tested memory; reading output data from the storage unit corresponding to the to-be-tested address of the to-be-tested memory; and comparing the to-be-tested data and the output data to obtain a test result of the to-be-tested memory. The self-test circuit disposed in the storage device is used to implement a memory test process. Thus, the dependency on automatic test equipment is reduced, thereby improving test speed and reducing test cost.

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Hefei, China

Li Ding