Huawei Technologies Co., Limited

Hon Hai Precision Industry Co., Ltd.

Hong-fu Jin Precision Industry (shenzhen) Co., Ltd.

Li Ding

Desheng Sun

Wei Zhang

Kang Wu

Jun Huang

Weifeng Liu

Zhigang Zhu

Jianbing Wang

Yongzhi Liu

Chunsheng Yang

Hongjun Bi

A bit block sending method includes generating at least one first bit block, where the at least one first bit block is used to feed back whether at least one first packet is correctly received, the at least one first bit block further includes a first sequence field, and the first sequence field is used to carry first sequence information of the at least one first packet, and sending the at least one first bit block.

Bit block sending method and apparatus

This application provides a data transmission method, a communication apparatus, and a communication system. The method includes: generating N ciphertext data flows, where a first ciphertext data flow is any one of the N ciphertext data flows. The first ciphertext data flow includes at least two first alignment markers AMs, at least two encryption parameter sets, and at least two ciphertext data segments. One ciphertext data segment and one encryption parameter set are included between every two first AMs. The at least two first AMs are used for data alignment of the N ciphertext data flows. The method further includes sending the N ciphertext data flows. The data transmission method may be applied to a physical layer of an optical module or a network device.

Data transmission method, communication apparatus, and communication system

Method and an apparatus are provided for indicating a fault status. The method includes: a first device determines N alignment marker AM groups, where the N AM groups include first indication information, the first indication information is used to indicate a fault status of R receiving logical lanes of the first device, and each of the N AM groups includes M pieces of alignment marker group lane AMGL information; and in an iperiod of N periods, the first device respectively sends M pieces of AMGL information constituting an iAM group to a second device over M transmitting logical lanes.

Method and apparatus for indicating fault status

A method includes: sending, by a first device, a first bit stream to a second device, where the first bit stream is sent over N logical lanes of a physical layer of the first device; sending, by the first device, a first trigger marker group to the second device, where the first trigger marker group is used to indicate that the sending of the first bit stream ends; and sending, by the first device, a second bit stream to the second device in response to the sending of the first trigger marker group, where the second bit stream is sent over P logical lanes of the physical layer of the first device, and both N and P are positive integers.

Ethernet data transmission method and communications device

Embodiments of the present invention provide a chip package structure and a chip packaging method, which is related to the field of electronic technologies, and can protect chips and effectively dissipate heat for chips. The chip package structure includes a substrate, chips, and a heat dissipating lid, where the chips include at least one master chip disposed on the substrate and at least one slave chip disposed on the substrate; the heat dissipating lid is bonded to the slave chip by using a heat conducting material, and the heat dissipating lid covers the at least one slave chip; and the heat dissipating lid includes a heat dissipating window at a position corresponding to the at least one master chip. The embodiments of the present invention are applicable to multi-chip packaging.

Chip package structure and chip packaging method

A multilayer circuit board is provided, which includes multiple core boards stacked together. The core board includes an insulation layer and at least one conductor layer attached together. The conductor layer includes a circuit. The core board has at least one identification conductor disposed at an edge of at least one conductor layer. The identification conductor forms an identification pattern on a side surface of the core board along a stacking direction of the core boards. The identification patterns of the multiple core boards are different from each other on the side surface of the multilayer circuit board along the stacking direction of the core boards. A manufacturing method of the multilayer circuit board is further provided.

Multilayer circuit board and manufacturing method thereof

A system and method for testing a Link Control Card (LCC) of a storage device includes a host, a middle plane (MP), a switch, and a testing device array. The host is connected to the testing device array for sending out command sets and receiving results. The MP is connected between the LCC and the testing device array. The switch determines the LCC to output hard reset signals and the hard reset signals are transferred to the testing device array via the MP. The testing device array includes a plurality of testing devices, and each of the testing devices includes a micro-controller unit (MCU); a connector being connected to the MCU, and coupled to the MP; an address setting unit being connected to the MCU, for setting an unique address of each of the testing devices; and a first interface being connected to the MCU for outputting results.

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Shenzhen, China

Li Ding