Taiwan Semiconductor Manufacturing Comp. Ltd.

National Taiwan University

Li-Chung Kuo

Ying-Ching Shih

Szu-Wei Lu

Kuan-Yu Huang

Jing-Cheng Lin

Sung-Hui Huang

Shang-Yun Hou

Long Hua Lee

Chen-Hua Douglas Yu

Ying-Da Wang

Chih-Wei Wu

Yu-Wei Chen

Kung-Chen Yeh

Chi-Hsi Wu

Hsien-Pin Hu

Hsing-Kuo Hsia

Chin-Fu Kao

Tsung-Yu Chen

Szu Wei Lu

Pu Wang

Wen-Hsin Wei

Chien-Yuan Huang

Heh-Chang Huang

Yushun Lin

Chih-Chieh Hung

Shin-Puu Jeng

Pai Yuan Li

Po-Hao Tsai

Li-Hui Cheng

Tsung-Fu Tsai

Jiun-Haw Lee

Hsien-Ju Tsou

Man-Kit Leung

Kuo-Huang Hsieh

Chao-Hui Kuo

Kuei-Hui Yang

Long-Hua Lee

Yi Chou

Kang-Jyun Peng

Jeh-Yin Chang

A method includes bonding a first package component over a second package component, dispensing a first underfill between the first package component and the second package component, and bonding a third package component over the second package component. A second underfill is between the third package component and the second package component. The first underfill and the second underfill are different types of underfills.

Packages with multiple types of underfill and method forming the same

An integrated circuit package and a method of forming the same are provided. The method includes attaching an integrated circuit die to a first substrate. A dummy die is formed. The dummy die is attached to the first substrate adjacent the integrated circuit die. An encapsulant is formed over the first substrate and surrounding the dummy die and the integrated circuit die. The encapsulant, the dummy die and the integrated circuit die are planarized, a topmost surface of the encapsulant being substantially level with a topmost surface of the dummy die and a topmost surface of the integrated circuit die. An interior portion of the dummy die is removed. A remaining portion of the dummy die forms an annular structure.

Integrated circuit package and method of forming same

A method for forming an underfill structure and semiconductor packages including the underfill structure are disclosed. In an embodiment, the semiconductor package may include a package including an integrated circuit die; an interposer bonded to the integrated circuit die by a plurality of die connectors; and an encapsulant surrounding the integrated circuit die. The semiconductor package may further include a package substrate bonded to the interposer by a plurality of conductive connectors; a first underfill between the package and the package substrate, the first underfill having a first coefficient of thermal expansion (CTE); and a second underfill surrounding the first underfill, the second underfill having a second CTE less than the first CTE.

Underfill structure for semiconductor packages and methods of forming the same

A method of forming a semiconductor device includes applying an adhesive material in a first region of an upper surface of a substrate, where applying the adhesive material includes: applying a first adhesive material at first locations of the first region; and applying a second adhesive material at second locations of the first region, the second adhesive material having a different material composition from the first adhesive material. The method further includes attaching a ring to the upper surface of the substrate using the adhesive material applied on the upper surface of the substrate, where the adhesive material is between the ring and the substrate after the ring is attached.

Semiconductor package and method of forming the same

3D semiconductor packages and methods of forming 3D semiconductor package are described herein. The 3D semiconductor packages are formed by mounting a die stack on an interposer, dispensing a thermal interface material (TIM) layer over the die stack and placing a heat spreading element over and attached to the die stack by the TIM layer. The TIM layer provides a reliable adhesion layer and an efficient thermally conductive path between the die stack and interposer to the heat spreading element. As such, delamination of the TIM layer from the heat spreading element is prevented, efficient heat transfer from the die stack to the heat spreading element is provided, and a thermal resistance along thermal paths through the TIM layer between the interposer and heat spreading element are reduced. Thus, the TIM layer reduces overall operating temperatures and increases overall reliability of the 3D semiconductor packages.

Thermal interface materials, 3D semiconductor packages and methods of manufacture

A method includes bonding a second package component to a first package component, bonding a third package component to the first package component, attaching a dummy die to the first package component, encapsulating the second package component, the third package component, and the dummy die in an encapsulant, and performing a planarization process to level a top surface of the second package component with a top surface of the encapsulant. After the planarization process, an upper portion of the encapsulant overlaps the dummy die. The dummy die is sawed-through to separate the dummy die into a first dummy die portion and a second dummy die portion. The upper portion of the encapsulant is also sawed through.

Dummy die placement without backside chipping

A method includes bonding a first and a second package component on a top surface of a third package component, and dispensing a polymer. The polymer includes a first portion in a space between the first and the third package components, a second portion in a space between the second and the third package components, and a third portion in a gap between the first and the second package components. A curing step is then performed on the polymer. After the curing step, the third portion of the polymer is sawed to form a trench between the first and the second package components.

Sawing underfill in packaging processes

Growing community of inventors

Taipei, Taiwan

Li-Chung Kuo