Taiwan Semiconductor Manufacturing Comp. Ltd.

Alpha Networks Inc.

Li-Chung Hsu

Sung-Yen Yeh

Chung-Hsing Wang

Jerry Chang-Jui Kao

King-Ho Tam

Hui-Zhong Zhuang

Jung-Chan Yang

Yung-Chen Chien

Tzu-Ying Lin

Yen-Pin Chen

Meng-Xiang Lee

Ho Che Yu

Shih-Hsien Yang

Chih-Wei Chao

Ravi Babu Pittu

Shih-Chi Lee

Yu-Hsin Kuo

Po-Wei Shih

Min-Chie Jeng

Chung-Min Fu

Chi-Yeh Yu

Ke-Wei Su

Chung-Kai Lin

Cheng Yuan Hsiao

Tai-Yu Cheng

Yi-Shun Huang

Ya-Chin Liang

Ting-Sheng Huang

Wai-Kit Lee

Jerry Kao

Juan-Yi Chen

An integrated circuit is provided and includes first transistors of a first circuit arranged in a first cell row having a first number of fin structures and a second transistor of a second circuit. The second transistor is coupled in parallel with a first element in the first transistors between first and second terminals of the first circuit, and arranged in a second cell row having a second number, different from the first number, of fin structures. The first element and the second transistor share a first gate extending in a first direction to pass through the first and second cell rows in a layout view. The second transistor is a duplication of the first element.

Integrated circuit in hybrid row height structure

Systems and methods for context aware circuit design are described herein. A method includes: identifying at least one cell to be designed into a circuit; identifying at least one context parameter having an impact to layout dependent effect of the circuit; generating, for each cell and for each context parameter, a plurality of abutment environments associated with the cell; estimating, for each cell and each context parameter, a sensitivity of at least one electrical property of the cell to the context parameter by generating a plurality of electrical property values of the cell under the plurality of abutment environments; and determining whether each context parameter is a key context parameter for a static analysis of the circuit, based on the sensitivity of the at least one electrical property of each cell and based on at least one predetermined threshold.

Systems and methods for context aware circuit design

A semiconductor device includes several first cell row an several second cell rows. The first cell rows extend in a first direction. Each of the first cell rows has a first row height. A first row of the first cell rows is configured for a first cell to be arranged. The second cell rows extend in the first direction. Each of the second cell rows has a second row height that is different from the first row height. At least one row of the second cell rows includes a portion for at least one second cell to be arranged. The portion has a third row height that is different from the first row height and the second row height.

Semiconductor device and integrated circuit in hybrid row height structure

A system includes a non-transitory storage medium encoded with a set of instructions and a processor. The processor is configured to execute the set of instructions. The set of instructions is configured to cause the processor to: obtain, based on a netlist of a circuit, values each corresponding to one of transistors included in the circuit; compare the values with a threshold value; in response to a comparison, generate an adjusted netlist of the circuit by adding redundant transistors; and determine, based on the adjusted netlist, one of layout configurations for the circuit. The layout configurations include first cell rows each having a first row height and second cell rows each having a second row height different from the first row height.

A semiconductor device includes several first cell rows extending in a first direction, each of the first cell rows having a first row height; several second cell rows extending in the first direction, each of the second cell rows having a second row height smaller than the first row height, wherein the first cell rows and the second cell rows are interlaced; a first cell arranged in a first row of the first cell rows; and at least one second cell arranged in at least one row of the second cell rows, wherein the at least one second cell abuts the first cell in a second direction different from the first direction, wherein the at least one second cell and at least one circuit component included in the first cell have the same operation configuration.

A method includes: identifying a timing path of a logic circuit; determining a Boolean expression at an internal node in the timing path; providing a DC vector having a plurality of forms; determining a Boolean value at the internal node for each of the forms based on the Boolean expression; determining a quantity of stressed transistors in the timing path for each of the forms separately based on the respective Boolean value; and determining a best-case form, associated with an aging effect of the logic circuit, and a worst-case form, associated with the aging effect, out of the forms based on the quantities of stressed transistors.

Method of determining a worst case in timing analysis

A cloud radio access network system includes remote signal sources, a baseband processing unit pool, an access management server, a software defined network controller and a network signal forwarder. Each remote signal source is configured to transmit an access signal. The baseband processing unit pool provides a baseband processing signal. The access management server provides an access state signal. Different maximum transmission rates are transmitted via the access state signal. When the baseband processing unit pool has authenticated one remote signal source, the baseband processing unit pool transmits an authentication notification signal to the access management server. Then, the access management server informs the software defined network controller according to the authentication notification signal to increase an upper limit of a signal transmission rate between the baseband processing unit pool and the authenticated remote signal source to a higher one of the maximum transmission rates.

Cloud radio access network system and control method thereof

A method includes identifying a timing path in a transistor level from a graph diagram; calculating a plurality of aging costs associated with the timing path based on a plurality of forms of a DC vector; identifying a first form, associated with a first aging cost of the aging costs, from the forms; and identifying a second form, associated with a second aging cost less than the first aging cost, from the forms.

Method of determing a worst case in timing analysis

A cloud radio access network system includes remote signal sources, a baseband processing unit pool, an access management server, a software defined network controller and a network signal forwarder. The software defined network controller is electrically connected to the access management server and the network signal forwarder. The network signal forwarder includes at least two network connectors, each of which is configured to be connected to one remote signal source or the baseband processing unit pool. The software defined network controller obtains connection relation between the network connectors and the remote signal sources or the baseband processing unit pool, and provides network resource information to the network signal forwarder according to the connection relation. The network signal forwarder establishes communication between one remote signal source and the baseband processing unit pool according to the network resource information.

A method for establishing an aging model of a device is provided. The device is measured to obtain degradation information of the device under an operating condition, wherein the device is a physical device. The degradation information is partitioned into a permanent degradation portion and an impermanent degradation portion. The impermanent degradation portion is differentiated by time to obtain a differential value. The aging model is obtained according to the differential value. When the differential value is greater than zero, a degradation of the device increases over time, and when the differential value is less than zero, the degradation of the device decreases over time.

Method for establishing aging model of device and analyzing aging state of device with aging model

A method performed by a processor, the method including preparing a netlist describing a first circuit including an active component; obtaining an original electrical characteristic of the active component, wherein an electrical characteristic of the active component is the original electrical characteristic in a condition that the active component has not been operated; obtaining an aged data describing a variation in the original electrical characteristic, wherein the variation is caused by operating the first circuit under a first mode and a second mode different from the first mode during a time period; providing a simulation result by simulating, based on an aged electrical characteristic, the first circuit operating under the first mode and the second mode during the time period, wherein the aged electrical characteristic is a combination of the original electrical characteristic and the variation.

Semiconductor circuit design and manufacture method

A method comprises providing a non-transitory, machine-readable storage medium storing a partial netlist of at least a portion of a previously taped-out integrated circuit (IC) layout, representing a set of photomasks for fabricating an IC having the IC layout such that the IC meets a first specification value. A computer identities a proper subset of a plurality of first devices in the IC layout, such that replacement of the proper subset of the first devices by second devices in a revised IC layout satisfies a second specification value different from the first specification value. At least one layout mask is generated and stored in at least one non-transitory machine readable storage medium, accessible by a tool for forming at least one additional photomask, such that the set of photomasks and the at least one additional photomask are usable to fabricate an IC according to the revised IC layout.

Layout modification method and system

A method includes identifying at least one local power segment of a circuit, estimating at least one performance parameter of the at least one power segment based on a computer-based simulation of the circuit, and changing a design of the circuit based on at least one electromigration avoidance strategy if the at least one parameter is greater than or equal to a threshold value. A data file representing the circuit is stored if the at least one parameter is less than the threshold value.

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Hsinchu, Taiwan

Li-Chung Hsu