Realtek Semiconductor Inc.

Li-Chung Chen

Yuan-Jih Chu

Chia-Chang Lin

Shieh-Hsing Kuo

Ching-Yao Su

Yung-Le Chang

Hsin-Yun Hu

Bo-Cheng Lin

Wei-Ting Lin

A multidrop network system includes N network devices including a master device and a plurality of slave devices. The N network devices synchronize their respective time zones in a synchronization phase, then jointly perform equalizer coefficient training in a training phase, and then obtain their respective transmission opportunities in turn in a data transmission phase. Each network device includes a channel equalizer trained in the training phase and used for processing data in the data transmission phase. In the training phase, the master device sends out a training notification to request the slave devices to enter the training phase; the master device performs the equalizer coefficient training after it transmits the training notification, and the slave devices perform the equalizer coefficient training after they receive the training notification. After the completion of the equalizer coefficient training, the master device sends out a beacon to start the data transmission phase.

Multidrop network system and network device

A signal processor includes a signal receiving circuit, a pre-processing circuit, a period acquisition circuit, and a decoding circuit. The signal receiving circuit is configured to receive an input signal. The pre-processing circuit is configured to generate a square wave signal according to the input signal. The period acquisition circuit is configured to capture several periods of the square wave signal. The several signal periods includes several signal period groups, and each of the several signal period groups includes at least two signal periods of the several signal periods. The at least two signal periods are adjacent to each other. The decoding circuit is coupled to the period acquisition circuit and is configured to perform decoding according to a time length and a number of times of voltage value change of the several signal period groups to obtain a decoding result.

Signal processor and signal processing method

A communication device is disclosed. The communication device includes a transceiver circuit, an echo canceler, and a processor. The transceiver circuit is configured to transmit a test signal to a channel. The echo canceler is configured to obtain a plurality of echo power of a reflected signal corresponding to the test signal. The processor is configured to obtain a plurality of positions on the channel according to a parameter value. The parameter value is N, a number of the plurality of positions is N, and the plurality of positions corresponds to the top N largest of the plurality of echo power. The echo canceler is further configured to eliminate part of the plurality of echo power corresponding to the plurality of positions according to the plurality of positions.

Communication device and echo cancellation method

An electronic system includes a feedforward equalizer, a feedback equalizer, an RFI canceler, and a control circuit. The feedforward equalizer and the feedback equalizer are configured to adjust the channel response of a transmission channel in the electronic system. The RFI canceler is configured to cancel the RFI presence in the electronic system. When the RFI canceler is off, the controller is configured to turn on the RFI canceler according to a signal error value before RFI cancelation, an error term of the electronic system, or an SNR of the electronic system.

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Zhubei, Taiwan

Li-Chung Chen