Taiwan Semiconductor Manufacturing Comp. Ltd.

TSMC China Company Limited

TSMC Nanjing Company, Limited

Li-Chun Tien

Hui-Zhong Zhuang

Ting-Wei Chiang

Lee-Chung Lu

Chih-Liang Chen

Ting Yu Chen

Pin-Dai Sue

Chung-Te Lin

Ta-Pen Guo

Guo-Huei Wu

Shun Li Chen

Jung-Chan Yang

Chi-Yu Lu

Tung-Heng Hsieh

Sheng-Hsiung Wang

Hsiang-Jen Tseng

Yung-Chin Hou

Po-Hsiang Huang

Sheng-Hsiung Chen

Wei-Yu Chen

Yi-Kan Cheng

Fong-yuan Chang

Shyue-Shyh Lin

XinYong Wang

Fong-Yuan Chang

Jung-Hsuan Chen

Yuan-Te Hou

Shang-Chih Hsieh

Huang-Yu Chen

Pochun Wang

Chien-Ying Chen

Hung-Jen Liao

Chung-Hsing Wang

Jerry Chang-Jui Kao

Ru-Gun Liu

Wei-Cheng Lin

Shih-Wei Peng

Yen-Huei Chen

Ken-Hsien Hsieh

Shao-Yu Chou

Kuo-Ji Chen

Chin-Hsiung Hsu

Wei-Ling Chang

Jiann-Tyng Tzeng

Chih-Hsin Ko

Chung-Cheng Wu

Min Cao

Hong-Chen Cheng

Chih-Yu Lai

Chun-Chen Chen

Shao-Huan Wang

Meng-Hung Shen

Yen-Pin Chen

Chia-Ming Hsu

Clement Hsingjen Wann

Sang Hoo Dhong

Cheng Hung Lee

Kuo-Hua Pan

Chin-Chou Liu

Chi-Lin Liu

Wen-Ju Preet Yang

Tsong-Hua Ou

Yen-Hung Lin

Cheng-I Huang

Gwan Sin Chang

Chang-Yu Wu

Zhe-Wei Jiang

Ho Che Yu

Chun-Fu Chen

Ching-Wei Tsai

Chan-Hong Chern

Fu-Lung Hsueh

Dian-Hau Chen

Wen-Hao Chen

Yi-Hsun Chiu

Shang-Wen Chang

Chin-Chang Hsu

Bo-Ting Chen

Min-Hsiung Chiang

Tzu-Ying Lin

Ching Fu Chang

Wei Yu Ma

Jhon-Jhy Liaw

Li-Jui Chen

Tsai-Sheng Gau

Yue-Der Chih

Chun-Kuang Chen

Wen-Chun Huang

Chiting Cheng

David Barry Scott

Jaw-Jung Shin

Cheng-Chung Lin

Tsung-Chieh Tsai

Yuh-Jier Mii

Wen-Li Cheng

Burn-Jeng Lin

Cliff Hou

Chen-Ming Hung

Chung-Ji Lu

Huan-Tsung Huang

A method of generating an IC layout diagram includes positioning a cell in the IC layout diagram relative to a first metal layer cut region alignment pattern and overlapping the cell with a first metal layer cut region. The cell includes a first metal layer region corresponding to one of a first or second mask set, the first metal layer cut region alignment pattern includes a sub-pattern corresponding to the one of the first or second mask set, and the first metal layer cut region corresponds to the sub-pattern.

Metal cut region location method

An integrated circuit includes a first gate electrode structure extending in a first direction. The integrated circuit includes a second gate electrode structure extending in the first direction and separated in a second direction from the first gate electrode structure. The integrated circuit includes a conductive feature. The conductive feature includes a first section electrically connected to the second portion, a second section electrically connected to the second gate structure, and a third section electrically connecting the first section and the second section, wherein the third section extends in a third direction angled with respect to both the first direction and the second direction.

Integrated circuit having angled conductive feature

An integrated circuit includes a first transistor of a first conductivity type including a first active area extending in a first direction; a second transistor of the first conductivity type including at least two second active areas extending in the first direction and a first gate stripe crossing the at least two second active areas; and a third transistor of a second conductivity type that is stacked on the second transistor and includes at least two third active areas arranged above the at least two second active areas. A top most boundary line of the first active area is aligned with a top most boundary line of one of the at least two third active areas in a layout view.

Integrated circuit

A method of generating a layout diagram of a semiconductor device includes populating a conductive layer M(h) with segment patterns representing corresponding conductive segments in the semiconductor device. The segment patterns including first and second power grid (PG) patterns and first routing patterns, where h is an integer and h≥1. Arranging long axes of the first and second PG patterns and the first routing patterns to extend in a first direction. Arranging the first and second PG patterns to be separated, relative to a second direction, by a PG gap having a midpoint. The second direction being substantially perpendicular to the first direction. Distributing the first routing patterns between the first and second PG patterns and substantially uniformly in the second direction with respect to the midpoint of the PG gap.

Method for generating a layout diagram of a semiconductor device including power-grid- adapted route-spacing

A semiconductor structure includes an isolation structure formed on a substrate, a gate-all-around transistor structure formed on the isolation structure, a via electrically coupled to a gate terminal of the gate-all-around transistor structure, and a buried conductive pad formed within the isolation structure and electrically coupled to the via. The buried conductive pad can extend through the isolation structure in two dimensions, such as in both a vertical dimension and a horizontal dimension. The semiconductor structure can provide advantages in terms of routing flexibility, among other possible advantages.

Buried pad for use with gate-all-around device

A system for processing a layout of a semiconductor device includes a processor, and a computer readable storage medium. The processor is configured to execute instructions to generate an active region layout pattern extending in a first direction, generate a plurality of gate layout patterns extending in a second direction different from the first direction, wherein the plurality of gate layout patterns extends across the active region layout pattern, generate a plurality of source/drain region layout patterns in the active region layout pattern on opposite sides of the plurality of gate layout patterns, generate a plurality of source/drain contact layout patterns overlapping the plurality of source/drain region layout patterns, and generate one or more mark layers. Each of the mark layers labels a corresponding source/drain contact layout pattern of the plurality of source/drain contact layout patterns and is usable to indicate a width of the corresponding source/drain layout pattern.

Integrated circuit layouts with source and drain contacts of different widths

An IC device includes first through third rows of fin field-effect transistors (FinFETs), wherein the second row is between and adjacent to each of the first and third rows, the FinFETs of the first row are one of an n-type or p-type, the FinFETs of the second and third rows are the other of the n-type or p-type, the FinFETs of the first and third rows include a first total number of fins, and the FinFETs of the second row include a second total number of fins one greater or fewer than the first total number of fins.

Integrated circuit fin structure

A method includes fabricating a first-voltage underlayer power rail conductively connecting to the source region of a first-type transistor and fabricating a second-voltage underlayer power rail conductively connecting to the source region of a second-type transistor. Each of the first-voltage and second-voltage underlayer power rails extends in a first direction. The method also includes patterning a first connection layer to form a first-voltage power rail and a second-voltage power rail extending in the second direction which is perpendicular to the first direction. The first-voltage power rail is directly connected with the first-voltage underlayer power rail through a first via-connector and the second-voltage power rail is directly connected with the second-voltage underlayer power rail through a second via-connector.

Power rail and signal conducting line arrangement

A method is provided, and including operations as below: forming multiple active areas extending in a first direction; forming multiple conductive patterns extending in a second direction different from the first direction and arranged in a first layer above the active areas; forming multiple gates extending parallel to the conductive patterns; and forming a first set of conductive lines extending in the first direction and arranged in three first metal tracks that are in a second layer above the first layer, wherein one of the first set of conductive lines is arranged in a middle track of the three first metal tracks, coupled to one of the gates and overlap a first shallow trench region between two of the active areas.

A method of designing a semiconductor device including the operations of analyzing a vertical abutment between a first standard cell block and a second cell block and, if a mismatch is identified between the first standard cell block and the second cell block initiating the selection of a first modified cell block that reduces the mismatch and a spacing between the first modified cell block and the second cell block, the first modified cell block comprising a first abutment region having a continuous active region arranged along a first axis parallel to an edge of the vertical abutment, and replacing the first standard cell block with the first modified cell block to obtain a first modified layout design and devices manufactured according to the method.

Reduced area standard cell abutment configurations

An integrated circuit includes a first transistor, a second transistor, a first power line, and a second power line. The first transistor has a first active region and a first gate structure, in which the first active region has a source region and a drain region on opposite sides of the first gate structure. The second transistor is below the first transistor, and has a second active region and a second gate structure, in which the second active region has a source region and a drain region on opposite sides of the second gate structure. The first power line is above the first transistor, in which the first power line is electrically connected to the source region of first active region. The second power line is below the second transistor, in which the second power line is electrically connected to the source region of second active region.

Integrated circuit and manufacturing method thereof

An IC structure includes a first cell and a first and second rail. The first cell includes a first and second active region and a first, a second and a third gate structure. The first active region having a first dopant type. The second active region having a second dopant type. The first gate structure extending in a second direction, overlapping the first or the second active region. The second gate structure extending in the second direction, and overlapping a first edge of the first or second active region. The third gate structure extending in the second direction, and overlapping at least a second edge of the first or second active region. The first rail extending in the first direction and overlapping a middle portion of the first active region. The second rail extending in the first direction and overlapping a middle portion of the second active region.

Integrated circuit structure

A method of making an integrated circuit includes dividing, in a first layer of an integrated circuit layout, a first arrangement of metal lines into a first set of metal lines and a second set of metal lines, wherein the first set of metal lines is between the second set of metal lines and a periphery of the integrated circuit layout, wherein the first arrangement of metal lines is configured to electrically connect to a plurality of contacts connected to a second layer of the integrated circuit layout after a manufacturing process. The method further includes adjusting a metal line perimeter of at least one metal line in the second set of metal lines to make a second arrangement of metal lines, wherein each adjusted metal line perimeter is separated from contacts in the second layer of the integrated circuit layout by at least a check distance.

Integrated circuit with constrained metal line arrangement, method of using, and system for using

A cell on an integrated circuit is provided. The cell includes: a fin structure; an intermediate fin structure connection metal track disposed in an intermediate fin structure connection metal layer above the fin structure, the intermediate fin structure connection metal track being connected to the fin structure; and a first intermediate gate connection metal track disposed in an intermediate gate connection metal layer above the intermediate fin structure connection metal layer, the first intermediate gate connection metal track being connected to the intermediate fin structure connection metal track. A first power supply terminal is connected to the first intermediate gate connection metal track.

Cell structure with intermediate metal layers for power supplies

An integrated circuit is provided and includes a multi-bit cell having multiple bit cells disposed in multiple cell rows. The bit cells include M bit cells, M being positive integers. A first bit cell of the bit cells and a M-th bit cell of the bit cells are arranged diagonally in different cell rows in the multi-bit cell. The multi-bit cell includes first to fourth cell boundaries. The first and second boundaries extend in a first direction and the third and fourth boundaries extend in a second direction different from the first direction. The first bit cell and a second bit cell of the bit cells abut the third cell boundary, and the first bit cell and a (M/2+1)-th bit cell of the bit cells abut the first cell boundary.

Multi-bit structure

Growing community of inventors

Tainan, Taiwan

Li-Chun Tien