Hewlett-packard Company

Hewlett-packard Development Company, L.P.

Li Ching Tsai

Daniel Krueger

Johnny Q Zhang

Charles E Moore

Travis N Blalock

Rajeev Badyal

Richard A Baumgartner

Larry S Metz

Ran-Fun Chiu

Sui-hing Leung

Thomas M Walley

Richard A Baugh

David B Hollenbeck

Robert A Zimmer

James S Ignowski

Hugh S Wallace

Kenneth R Stafford

Karsten Guthridge

Protik Mia

Floyd E Moore

Richard M Blumberg

Clock circuitry supplies synchronized clock waves to loads on plural integrated circuit chips. The clock circuitry couples the synchronized clock waves to regions of the chips. There is a first clock wave route in a first direction from a first chip to a second chip and a second clock wave route in a second direction from the second chip to the first chip. The routes have substantially the same geometry and are in close proximity to each other so they have substantially the same effects on clock waves propagating therein in opposite directions. A phase detector and lowpass filter on the first chip responds to (1) a clock wave source and (2) a clock wave derived on a chip other than the first chip, to supply, via a common mode line, a control for voltage controlled delays of the chips other than the third chip.

Clock circuitry on plural integrated circuits

A high speed incrementer/decrementer design is presented that computes the propagate, generate, and kill signals which are used to compute carries and sums from the incrementer inputs. By setting one input to &ldquo;0&rdquo; and the carry-in to &ldquo;1&rdquo;, the adder is used as an incrementer. In the design of the invention, a bit-wise decision is made whether to complement the input bit or not. The design also allows decrementing and supports both unsigned and 2's complement number representations.

High speed incrementer/decrementer

Integrated circuit clock circuitry includes several clock nodes at different locations on a chip. Each node includes a clock wave input, a clock wave output and feedback circuitry for maintaining a predetermined phase relation between clock waves at the clock wave inputs and outputs. The clock wave input of one of the nodes is directly responsive to a clock wave of a clock wave source. A clock coupling circuit connected between each of the clock wave inputs (except the clock wave input of the node directly responsive to the clock wave source) and each of the clock wave outputs couples clock waves from the clock wave output of a first node to a clock wave input of a second node. Each of the coupling circuits includes feedback circuitry for maintaining a predetermined phase relation between clock waves the first node supplies to the coupling circuit and derived by the coupling circuit. A measure of clock wave skew of the integrated circuit chip is obtained by connecting a clock coupling circuit and a separate node in a path extending between the most distant nodes on the chip. The path includes a phase detector responsive to clock waves supplied to the distantly spaced node and the node of the path extending between the most distant nodes on the chip.

Clock distribution circuitry to different nodes on integrated circuit with clock coupling circuitry to maintain predetermined phase relation between output and input of adjacent nodes

A ring-type signal controlled oscillator comprising a series of active delay elements, each including a respective differential pair of transistors. The inputs and outputs of the differential pair transistors are interconnected in a closed ring to produce oscillations at a frequency determined by the delay of each delay element. The differential pair of transistors further has a pair of current source inputs for controlling an amount of delay of the delay element, and a pair of load inputs for stabilizing the amount of delay. The invention advantageously provides high frequency operation with substantially symmetric rise and fall time, while limiting spread in oscillation frequency and spread in amplitude in relation to fabrication process variability and power supply variability.

Delay elements arranged for a signal controlled oscillator

A digital circuit for counting the number of zeroes or ones in a data word comprising a plurality of series paths leading to one-hot encoded outputs. Each one-hot encoded output indicates a different number of like signals in the input data word. One of the plurality of series paths is activated by connecting the series path from an input power rail to the one-hot output. A series path is connected through a plurality of transfer gates, each controlled by either a single bit of the input data word or its complement. The series paths may be optimized to share transfer gates by interconnecting them in a tree or lattice structure. Subsections of the input data word may be counted separately in independent tree or lattice structures, then combined in subsequent combinational stages of the circuit. The resulting one-hot encoded count of like signals may then be binary encoded by a final stage of the counting circuit.

Digital circuit to count like signals in a data word

A test coverage tool determines the adequacy of a set of test vectors for a state simulator for exercising logic paths in a logic circuit design. The speed coverage tool generally compares state data from a state simulator and timing data from a timing simulator in order to validate whether a test vector covers a simulated timing path. In architecture, the speed coverage tool includes first logic configured to acquire state data from the logic circuit design that has been produced by a state simulator based upon test vectors. Second logic associated with the tool obtains timing data concerning one or more logic paths of the logic circuit design that has been produced using a timing simulator. Third logic associated with the test coverage tool is configured to determine a transition score by comparing the timing data with the state data. The score is indicative of the adequacy of a set of test vectors. Another feature of the test coverage tool involves analysis of sensitization data, or logic state information regarding internal nodes that should be set to particular logic states in order to enable particular logic paths. A sensitization score can be produced to indicate the extent to which sensitization data matches. Analysis of the sensitization data by the test coverage tool results in more accurate analysis and assessment of coverage.

Speed coverage tool and method

An analog, fully integrated, partial response maximum likelihood (PRML) read channel utilizing a high-performance analog delay line, an analog adaptive equalizer and an analog Viterbi detector is provided, resulting in saved space, performance gains, and lower power consumption. For signal detection and reconstruction used in read operations, the partial response maximum likelihood (PRML) read channel includes a variable gain amplifier coupled to a lowpass filter for input to an adaptive analog equalizer. The adaptive analog equalizer comprises an analog delay line and an analog feedforward equalizer (FFE). An analog Viterbi detector employs maximum-likelihood sequence estimation (MLSE) techniques to performs the signal detection function. A decoder/descrambler produces a final reconstructed signal. The analog implementation of a partial response maximum likelihood (PRML) read channel also includes a scrambler/encoder coupled to a write precompensation circuit for output to a separate write head.

Analog implementation of a partial response maximum likelihood (PRML)

A dual adjust current-controlled phase locked loop is provided for allowing multiple-gain frequency acquisition of a signal. The dual adjust current-controlled phase locked loop includes a phase detector responsive to a reference signal and a synthesized signal for producing a phase error signal; a controller responsive to the phase error signal for generating coarse and fine adjust control signals; and a dual adjust current-controlled oscillator responsive to the coarse and fine adjust control signals for adjusting the oscillating frequency of the synthesized signal. The dual adjust current controlled oscillator includes a differential current controlled ring oscillator comprising a series of delay elements. Each delay element includes a high gain circuit responsive to the coarse adjust control signal and a low gain circuit responsive to the fine adjust control signal.

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Ft. Collins, CO, United States of America

Li Ching Tsai