Taiwan Semiconductor Manufacturing Comp. Ltd.

Li-Chih Chao

Li-Te S Lin

Chia-Shiung Tsai

Jen-Cheng Liu

Tsang-Jiuh Wu

Jhon-Jhy Liaw

Chao-Cheng Chen

Yuan-Chang Huang

Jin-Yuan Lee

Ming-Huei Lui

Dun-Nian Yaung

Bao-Ru Young

Huan-Just Lin

Shou-Gwo Wuu

Hua-Tai Lin

Chen-Nan Yeh

Chu-Yun Fu

Jian-Hong Chen

Jiing-Feng Yang

Kuo Ching Huang

Shwangming Jeng

Yi-Chen Huang

Yung-Kuan Hsiao

Chao-Chen Chen

Bang-Chien Ho

Ching-Hui Ma

Shyue-Sheng Lu

Chi-Shiung Tsai

A method of fabricating semiconductor devices using dual damascene processes to form plugs in the via holes composed of various high etch materials and bottom anti-reflection coating (BARC) materials. After via hole etch, a layer of high etch rate plug material is spin coated to fill the via holes. Next, a layer of photoresist is applied. The photoresist is then exposed through a mask and developed to form an etch opening. Using the remaining photoresist as an etch mask and with a bottom anti-reflection coating (BARC) as protection, the oxide or low k layer is etched to form subsequent wiring. The etch step is known as a damascene etch step. The remaining photoresist is removed and the trench/via openings are filled with metal forming inlaid metal interconnect wiring and contact vias.

Dual damascene process

A method for forming a dual damascene opening comprising the following steps. A structure having an exposed conductive structure formed therein is provided. An etch stop layer is formed over the structure and the exposed conductive structure. A dielectric layer is formed over the etch stop layer. A hard mask layer is formed over the dielectric layer. The hard mask layer is patterned to form a partially opened hard mask layer. The partially opened hard mask layer having a trench area and a via area. The partially opened hard mask layer within the via area is patterned to form a partial via opened hard mask layer. Simultaneously, the partial via opened hard mask layer within both the trench area and the via area are etched and removed, and the dielectric layer within the via area is partial etched to form a partially opened dielectric layer to: expose a portion of dielectric layer within the trench area; and form a partial via within the partially opened dielectric layer. The partially opened dielectric layer is etched: within the trench area to form a trench; and within the via area to form a final via exposing a portion of etch stop layer. The trench and the final via forming the dual damascene opening.

Partial via hard mask open on low-k dual damascene etch with dual hard mask (DHM) approach

A plasma etch process for organic low-k dielectric layers using NH only, or NH /H or NH /H gases. A low k dielectric layer is formed over a substrate. A masking pattern is formed over the low k dielectric layer. The masking pattern has an opening. Using the invention's etch process, the low k dielectric layer is etched through the opening using the masking pattern as an etch mask. In a first embodiment, the etch process comprises: etching the low k dielectric layer by applying a plasma power and flowing only NH gas. In a second embodiment, the etch process comprises: etching the low k dielectric layer by applying a plasma power and flowing only NH /H gas. In a third embodiment, the etch process comprises: etching the low k dielectric layer by applying a plasma power and flowing only NH /N gas. The invention's NH containing plasma etch etches organic Low k materials unexpectedly fast. The invention's NH only etch had a 30 to 80% high etch rate than N /H etches of low-k materials like Silk&trade;.

Organic low K dielectric etch with NH3 chemistry

A novel etching method for preventing spiking and undercutting of an ultra low-k material layer in damascene metallization is described. A region to be contacted is provided in or on a semiconductor substrate. A liner layer is deposited overlying the region to be contacted. An ultra low-k dielectric layer is deposited overlying the liner layer. A damascene opening is etched through the ultra low-k dielectric layer to the liner layer overlying the region to be contacted wherein this etching comprises a high F/C ratio etch chemistry, high power, and low pressure. The liner layer within the damascene opening is etched away to expose the region to be contacted wherein this etching comprises a high F/C ratio etch chemistry, low power, and low pressure to complete formation of a damascene opening in the fabrication of an integrated circuit device.

Prevention of spiking in ultra low dielectric constant material

An improved method of patterning photoresist during formation of damascene structures is provided which involves a process that is resistant to poisoning from adjacent layers. An inert resin is used to fill vias in a damascene stack. Then a second stack comprised of an underlayer, a non-photosensitive Si-containing layer, an ARC, and a photoresist are formed on the first stack. A trench pattern formed in the photoresist is etch transferred into the first stack. The Si-containing layer that is preferably a spin-on material can be optimized for thermal and etch resistance without compromising lithographic properties since it is not photosensitive. The state of the art photoresist provides a large process window for printing small features with no scum. The inert resin, underlayer, and silicon containing layers are independent of exposure wavelength and can be readily implemented into existing or future manufacturing schemes.

Method of dual damascene patterning

A method of bi-layer top surface imaging, comprising the following steps. A structure having a lower layer formed thereover is provided. An upper silicon-containing photoresist layer is formed upon the lower layer. The upper silicon-containing photoresist layer is selectively exposed to form upper silicon-containing photoresist layer exposed portions. The upper silicon-containing photoresist layer exposed portions and the portions of the lower layer below the upper silicon-containing photoresist layer exposed portions are removed using an O -free N /H plasma etch.

N2/H2 chemistry for dry development in top surface imaging technology

A method for etching a dielectric layer comprising the following steps. A structure having a low-k dielectric layer formed thereover is provided. A DARC layer is formed over the low-k dielectric layer. A patterned masking layer is formed over the DARC layer. Using the patterned masking layer as a mask, the DARC layer and the low-k dielectric layer are etched employing an CH F /O /N /Ar etch chemistry.

High selectivity, low etch depth micro-loading process for non stop layer damascene etch

A new method is provided for the creation of an opening over which the second electrode of a MIM capacitor is to be deposited. The first electrode of the MIM is created in a first layer of Fluorine doped Silicon dioxide (SiO ) Glass (FSG) . A layer of insulation comprising silicon nitride is deposited over the surface of the first electrode. A second layer of Fluorine doped Silicon dioxide (SiO ) Glass (FSG) is deposited over the surface of the layer of silicon nitride, an etch stop layer of silicon nitride is deposited over the surface of the second layer of FSG. The layers of etch stop and the second layer of FSG are patterned and etched using a dry etch, stopping on the layer-of insulation and exposing the surface of the layer of insulation. Next-and of critical importance to the invention is a step of photoresist ashing and oxidation of the surface of the layer of silicon nitride. The layer of photoresist can now be removed while concurrently, using a wet strip, the layer of silicon nitride oxidation is removed from the surface of the layer of silicon nitride. The process of creating a MIM capacitor can then proceed by creating the second electrode of the MIM capacitor.

CU second electrode process with in situ ashing and oxidation process

A method of cleaning a low-k material etched opening, comprising the following steps. A semiconductor structure having an exposed device therein is provided. An etch stop layer is formed over the semiconductor structure and the exposed device. A layer of low-k material is formed over the etch stop layer semiconductor structure and device. A patterned layer of photoresist is formed over the low-k material layer. The patterned photoresist layer is used as a mask to etch low-k material layer is etched to form an opening exposing at least a portion of the etch stop layer over the device. The patterned photoresist layer is removed by a low temperature ashing process at a temperature from about 23 to 27&deg; C., and more preferably about 25&deg; C. (room temperature). The exposed portion of the etch stop layer over the device is removed to expose the underlying device by a low pressure, low bias etching process at a pressure from about 8 to 12 milli-Torr and a bias power from about 25 to 35 W. The exposed underlying device and the opening are cleaned by removing any remaining low pressure, low bias etch polymer and etch residue by a fully dry-type cleaning process using an H He gas.

Method of cleaning a copper/porous low-k dual damascene etch

Using this special dual damascene process, interconnect conducting lines and via contacts are formed which have low parasitic capacitance (low RC time constants). The invention incorporates the use of thin etch stop or etch barrier layers. The key process steps of this invention are a special partial via hole etch and a special via hole liner. The Prior Art dual damascene processes are generally composed of a thick via etch stop layer to avoid damaging underlying Cu during via patterning, as well as, a thick trench etch stop layer to avoid via hole facet during trench patterning. Thick etch stop layers are undesirably due to high dielectric constant values compared with silicon oxide, the intermetal dielectric (IMD). Therefore, the thickness of stop-layer should be reduced to minimize the circuit (RC) time constant delay. In general, there are two main approaches for dual damascene etching. One of the main approaches use self-aligned dual damascene (SADD) etching which requires a thick trench etching stop-layer thickness. The other approach use counter-bore method which requires a thick via etching stop-layer thickness. This invention describes a novel dual damascene process which can minimize the thickness of both via and trench etching stop-layer, while avoiding deleterious damage to the underlying to and via facet profile during via and trench etching.

Dual damascene process to reduce etch barrier thickness

A method is provided for forming dual damascene structures with a partial hard mask through a judicious use of partial opening or etching of the mask which simplifies the dual damascene process, and makes it especially suitable for low-k dielectric materials in advanced sub-micron technologies capable of forming features approaching less than 0.10 micrometers (&mgr;m). This is accomplished by forming a hard mask over a low-k dielectric layer. The hard mask is first opened partially to form a trench, and later again to form a via opening. The via opening is next extended into the low-k dielectric layer, followed by etching further the partial trench into the hard mask, and then transferring the trench pattern into the dielectric layer while at the same time extending the via opening to the underlying metal layer.

Partial hard mask open process for hard mask dual damascene etch

A method is described for cleaning freshly etched dual damascene via openings and preparing them for copper fill without damage or contamination of exposed organic or other porous low-k insulative layers. The method is entirely dry and does not expose the porous materials to contamination from moisture or solvents. The method is effective for removing all traces of residual polymer deposits from an in-process substrate wafers after via or damascene trench etching. The method employs an in-situ three-step treatment comprising a first step of exposing the electrically biased substrate wafer to a O,/N,ashing plasma to remove photoresist and polymers, a second step immediately following the first step of remove silicon nitride etch stop layers, and a final step of treating the wafer with H,/N,to remove copper polymer deposits formed during nitride removal. The H,/N,plasma is capable of removing the difficult polymer residues which are otherwise only removable by wet stripping procedures. The H,/N,plasma is not harmful to exposed porous low-k dielectric layers as well as copper metallurgy.

Fully dry post-via-etch cleaning method for a damascene process

The present invention provides a method for monitoring a self-aligned contact (SAC) etching process. A wafer with an oxide layer serves as an oxide control wafer. The oxide layer is formed on the substrate. The oxide control wafer and a SAC wafer with SAC structure are simultaneously treated with a SAC etching process in an etching chamber with the same etching recipe. A contact hole is formed by etching the oxide layer of the oxide control wafer after the SAC etching process. The depth of a profile transition point and the depth of etching stop for the oxide control wafer can be observed by cross-section SEM. The profile transition depth in the oxide control wafer corresponds to the etching thickness of S,N corner loss in the SAC wafer. Therefore, the profile transition depth and the depth of etching stop in the oxide control wafer can be used to monitor the etching chamber condition.

Method for monitoring self-aligned contact etching

A self-aligned structure and method of etching contact holes in the self-aligned structure are described. The dielectric materials, etching methods, and etchants are chosen to provide high selectivity etching. The structure comprises an electrode with a silicon oxy-nitride cap and silicon oxy-nitride spacers on the sidewalls of the electrode and the cap. An etch stop layer of silicon nitride is deposited over the substrate covering the spacers and cap. A layer of silicon oxide is deposited over the etch stop layer. Etching methods and etchants are used which provide a ratio of the etching rate of silicon oxide to the etching rate of silicon nitride or silicon oxy-nitride of at least eight and a ratio of the etching rate of silicon nitride to the etching rate of silicon oxy-nitride of at least two.

Self-aligned contact structures using high selectivity etching

A method was achieved for making improved self-aligned contacts (SAC) to a patterned polysilicon layer, such as gate electrodes for FETs. Lightly doped source/drain areas are implanted. A second insulating layer is deposited and etched back to form first sidewall spacers. A silicon nitride etch-stop layer and a first interpolysilicon oxide (IPO1) layer are deposited. First SAC openings are etched in the IPO1 layer to the etch-stop layer, and concurrently openings are etched for the gate electrodes, eliminating a masking step. The etch-stop layer is etched in the SAC openings to form second sidewall spacers that protect the first sidewall spacers during BOE cleaning of the contacts. A patterned polycide layer is used to make SACs and electrical interconnections. A second IPO layer is deposited to provide insulation, and an interlevel dielectric layer is deposited. Second SAC openings are etched to the etch-stop layer for the next level of metal interconnections, while the contact openings to the gate electrodes are etched to completion. The etch-stop layer is etched in the second SAC openings to form second sidewall spacers to protect the first sidewall spacers during cleaning. Metal plugs are formed from a first metal in the second SAC openings and in the openings to the gate electrodes. A second metal is patterned to complete the structure to the first level of metal interconnections.

Growing community of inventors

Yang Mei, Taiwan

Li-Chih Chao