Taiwan Semiconductor Manufacturing Comp. Ltd.

Li-Chi Chen

Hsin-Hui Lee

Chao-Yuan Su

Chia-Fu Lin

Yen-Ming Chen

Kai-Ming Ching

Yeng-Ming Chen

Hao-Chih Tien

Kai-Ming Chin

A process including providing a semiconductor device including a bond pad, and an under bump metallurgy overlying the bond pad. Forming a solder structure over the under bump metallurgy, and wherein the solder structure includes an outer layer including tin oxide. Producing a plasma from at least one of CF , SF , and H and exposing the solder structure to the plasma. Heating the solder structure and cooling the same to provide a solder bump on the semiconductor device.

Fluxless bumping process using ions

A method of fabricating a solder bump including the following steps. A UBM over a substrate.having an exposed pad portion is provided. The UBM being in electrical contact with the pad portion. A first patterning layer is formed over the UBM. The first patterning layer including a photosensitive material sensitive to light having a first wavelength. A second patterning layer is formed over the first patterning layer. The second patterning layer including a photosensitive material sensitive to light having a second wavelength. The first patterning layer is selectively exposed with the light having the first wavelength, leaving a first unexposed portion substantially centered over the pad portion between first exposed portions. The second patterning layer is selectively exposed with the light having the second wavelength, leaving a second unexposed portion wider than, and substantially centered over, the first unexposed portion of the exposed first patterning layer. The second unexposed portion of the exposed second patterning layer being between exposed portions. The second unexposed portion of the exposed second patterning layer and the first unexposed portion of the exposed first patterning layer are removed to form opening. A solder plug is formed within the opening. The exposed portions of the exposed first patterning layer and the exposed portions of the exposed second patterning layer are removed. The solder plug is reflowed to form a solder bump.

Method to improve reliability for flip-chip device for limiting pad design

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Taipei, Taiwan

Li-Chi Chen