United Microelectronics Corp.

Vanguard International Semiconductor Corporation

Other

Li-Che Chen

Hui-Min Wu

Jui-Chun Chang

Bang-Chiang Lan

Ming-I Wang

Chien-Hsin Huang

Hsiung-Shih Chang

Tzung-I Su

Hsing-Chao Liu

Te-Yuan Wu

Chien-Hsien Song

Tzung-Han Tan

Chung-Yi Chiu

Chia-Hao Lee

Kuo-Yuh Yang

Chia-Huei Lin

Min-Chih John Hsuan

Manoj Kumar

Chang-Sheng Hsu

Min Chen

Meng-Jia Lin

Kuan-Yu Wang

Chao-An Su

Yan-Da Chen

Kun-Che Hsieh

Chia-Wen Lien

Tsung-Hsi Ko

Chih-Wei Lin

Chih-Chung Wang

Nien-Chung Li

Chien-Wei Chiu

Shu-Wei Hsu

Francois Hebert

Ching-Wei Teng

Tzu-Hsuan Chen

Hung-Chih Tan

Ying-Kai Chou

Fu-Chun Chien

Chih-Chun Pu

Yu-Ting Yeh

Kuan-Wen Lu

Chih-Chong Wang

Ming-Sheng Hsu

A semiconductor structure is provided. The semiconductor structure includes a substrate, a gate disposed on the substrate, a source disposed in the substrate and located on one side of the gate, a drain disposed in the substrate and located on another side of the gate, and a gate extending portion disposed on the substrate and located between the gate and the drain. The doping type of the gate is the opposite of that of the gate extending portion.

Semiconductor structures

A MEMS structure includes a substrate, an inter-dielectric layer on a front side of the substrate, a MEMS component on the inter-dielectric layer, and a chamber disposed within the inter-dielectric layer and through the substrate. The chamber has an opening at a backside of the substrate. An etch stop layer is disposed within the inter-dielectric layer. The chamber has a ceiling opposite to the opening and a sidewall joining the ceiling. The sidewall includes a portion of the etch stop layer.

MEMS structure with an etch stop layer buried within inter-dielectric layer

A capacitor structure includes a first electrode plate disposed on a substrate, a first capacitor dielectric layer disposed on the first electrode plate, and a second electrode plate disposed on the first capacitor dielectric layer. A portion of the first electrode plate extends beyond an end of the second electrode plate to form a step. The capacitor structure also includes an etching stop layer, an inter-metal dielectric layer, a first via and a second via. The etching stop layer is disposed on the second electrode plate. The inter-metal dielectric layer covers the etching stop layer, the second electrode plate, the first capacitor dielectric layer and the first electrode plate. The first via penetrates through the inter-metal dielectric layer to contact the first electrode plate at the portion extending beyond the second electrode plate. The second via penetrates through the inter-metal dielectric layer to contact the second electrode plate.

Capacitor structures and methods for fabricating the same

A trench isolation structure is provided. The trench isolation structure includes a substrate. A polygonal trench is disposed in the substrate. An insulating material is disposed in the polygonal trench, and a polygon top-side contact structure is disposed in the polygonal trench and surrounded by the insulating material. The polygon top-side contact structure has the same shape as the polygonal trench from a top view. A method for forming the trench isolation structure is also provided.

Trench isolation structures and methods for forming the same

A semiconductor device and a method for forming the same are provided. The method includes forming a patterned mask on a substrate, wherein the patterned mask includes a pad oxide layer and a silicon nitride layer over the pad oxide layer. The method also includes forming a trench in the substrate by performing a first etching process on the substrate through an opening of the patterned mask and forming a dielectric material layer in the trench, in the opening, and on the patterned mask. The method further includes performing a planarization process to remove the dielectric material layer outside of the trench, and performing a heat treatment process to form an oxidized portion at the interface of the pad oxide layer and the substrate and adjacent to the dielectric material layer.

Semiconductor devices and methods for forming the same

A semiconductor device includes a via structure penetrating through a substrate, a top metal layer and an electronic component over the via structure, and a bottom metal layer and another electronic component below the via structure. The via structure includes a through hole penetrating from a first surface to an opposite second surface of a substrate, a filling insulating layer within the through hole, a first conductive layer, which is within the through hole and surrounds the filling insulating layer, wherein a portion of the first conductive layer is below the filling insulating layer and at the bottom of the through hole. The via structure further includes a first insulating layer, which is on the sidewalls of the through hole and surrounds the first conductive layer.

Semiconductor devices, via structures and methods for forming the same

A method for forming an isolation block of a semiconductor device includes providing a semiconductor substrate, performing an etching process to form a plurality of trenches which are parallel to each other in the semiconductor substrate, wherein a plurality of strip structures are between the trenches. The strip structures and the trenches occupy a first region in the semiconductor substrate, and the strip structures are arranged staggered with the trenches. The method further includes performing a thermal oxidation process, such that the strip structures are oxidized to form a plurality of oxidized portions, wherein the oxidized portions extended into the trenches and connected to each other to form an isolation block in the semiconductor substrate.

Methods for forming isolation blocks of semiconductor devices, semiconductor devices and methods for manufacturing the same

A method for manufacturing a semiconductor device includes forming a first gate structure on a semiconductor substrate. The first gate structure includes a first gate dielectric layer and a first gate electrode layer formed thereon. The method also includes forming an insulating material layer on the semiconductor substrate, wherein the semiconductor substrate and the first gate structure are covered by the insulating material layer. The method further includes removing a portion of the insulating material layer in a high-voltage element region to form a second gate dielectric layer in the high-voltage element region on the semiconductor substrate, and forming a second gate electrode layer on the second gate dielectric layer.

Semiconductor devices and methods for manufacturing the same

A semiconductor device includes a through-substrate via structure, a first metal layer, an electronic component over the through-substrate via structure, a second metal layer and another electronic component below the through-substrate via structure. The through-substrate via structure includes a through hole penetrating from a first surface to an opposite second surface of a semiconductor substrate, and an acute angle is included between a sidewall of the through hole and the second surface on a side of the semiconductor substrate. The through-substrate via structure also includes a conductive layer that fills the through hole, and a semiconductor layer disposed in the through hole and interposed between the conductive layer and the semiconductor substrate.

Semiconductor devices, through-substrate via structures and methods for forming the same

A fuse element includes a metal layer disposed on a substrate. The metal layer includes an intermediate segment, a first block and a second block. The first block and the second block are electrically connected to two respective ends of the intermediate segment. The fuse element also includes a dielectric layer covering the intermediate segment, the first block and the second block, a first passivation layer disposed on the dielectric layer, and a second passivation layer disposed on the first passivation layer. The fuse element further includes an opening penetrating through the first passivation layer, the second passivation layer and a portion of the dielectric layer, and located above the intermediate segment. In addition, a protective film is disposed on a bottom and a portion of a sidewall of the opening, and covers the first passivation layer exposed by the opening.

Fuse elements and methods for forming the same

A vertical diode is provided. The vertical diode includes a high-voltage N-type well region in a substrate, and two P-doped regions spaced apart from each other in the high-voltage N-type well region. The vertical diode also includes an N-type well region in the high-voltage N-type well region, and an N-type heavily doped region in the N-type well region. A plurality of isolation structures are formed on the substrate to define an anode region and a cathode region. There is a bottom N-type implanted region under the high-voltage N-type well region corresponding to the anode region. The bottom N-type implanted region directly contacts or partially overlaps the high-voltage N-type well region. A method for fabricating a vertical diode is also provided.

Vertical diode and fabrication method thereof

A method of forming a MEMS structure, in which an etch stop layer is formed to be buried within the inter-dielectric layer and, during an etch of the substrate and the inter-dielectric layer from backside to form a chamber, the etch stop layer protect the remaining inter-dielectric layer. The chamber thus formed has an opening at a backside of the substrate, a ceiling opposite to the opening, and a sidewall joining the ceiling. The sidewall may further include a portion of the etch stop layer.

Method for forming MEMS structure with an etch stop layer buried within inter-dielectric layer

A top-side contact structure is provided. The top-side contact structure includes a substrate. The substrate includes a first semiconductor layer, an insulating layer on the first semiconductor layer, and a second semiconductor layer on the insulating layer. The top-side contact structure also includes a first trench and a second trench formed in the second semiconductor layer and respectively extending along a first direction and a second direction. The first trench and the second trench connect to each other at an intersection point. The top-side contact structure also includes an insulating material filling the first trench and the second trench. The top-side contact structure also includes a contact plug formed at the intersection point and directly contacting the first semiconductor layer. A method for fabricating a top-side contact structure is also provided.

Top-side contact structure and fabrication method thereof

A method for supporting a semiconductor wafer includes providing a device wafer to a magnetizable ring, providing a magnetizable carrier to the device wafer, and magnetizing the magnetizable ring and the magnetizable carrier to form a magnetized clamp having a magnetized ring and magnetized carrier. The magnetized clamp securely clamps the device wafer therebetween.

Method for supporting semiconductor wafer and wafer supporting assembly

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Hsinchu, Taiwan

Li-Che Chen