E-systems, Inc.

Lex A Scott

William H Mosley, Jr

Carl F Andren

Robert S Gordy

A recovery loop includes an analog circuit that mixes a fixed frequency signal from a temperature controlled oscillator (20) with an IF input to produce product signals corresponding to the quadrature components of data signals with frequency offset. A digital complex multiplier (32) is responsive to the product signals and to the output of a number controlled oscillator (34) to produce a digital output corresponding to the data signals. The output of the number controlled oscillator (34) is controlled by a digital phase lock loop.

Digital baseband carrier recovery circuit

A phase lock loop (10) includes a frequency and phase preset network for presetting a local oscillator (20) in substantial synchronism with a carrier signal. The preset network utilizes time delayed output signals from split or double correlators (32, 34, 36, 38) to determine a change in the phase angle between the local oscillator signal and the carrier signal for a known time period to determine the frequency of the local oscillator signal relative to the carrier signal frequency. The preset network determines the phase of the local oscillator signal relative to the carrier signal phase utilizing the summed output of one split correlator (32 and 34) and of another split correlator (36 and 38).

Preset network for a phase lock loop

A biphase shift keyed modulated carrier is input to an analog delay line having a plurality of sampling taps time spaced along the line. The modulated input carrier is sampled at a rate four times the carrier frequency to produce amplitude samples of the input. The taps of the delay line are divided into two groups comprising alternate tap sets and the amplitude samples of each group are summed for decoding the I and Q channels of a modulated carrier. The summed signal of each of the channels is input to an individual sample and hold circuit which aliases the carrier frequency to baseband. The output of the first sample and hold circuit of each channel is provided to a second sample and hold circuit for the respective channels. The second sample and hold circuit of each channel is clocked at a data rate derived from a bit timing loop. An estimation of the data is produced by each of the second sample and hold circuits with the data produced by the second sample and hold circuit of one channel providing a recovered carrier signal output. Further, the data produced by each of the second sample and hold circuits, after inversion in one line by means of an inverting amplifier, is input to a phase comparator. The output of the phase comparator is filtered and used to drive a voltage controlled oscillator that generates the clock pulses to operate the first sample and hold circuits and also to clock the delay line.

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St. Petersburg, FL, United States of America

Lex A Scott