Signetics

Lewis K Russell

Richard S Muller

Tich T Dao

David Kleitman

Patrick A Tucci

Edward J McCluskey

In a method of configuring an integrated circuit provided in a semiconductor body having a surface and spaced semiconductor circuits formed in the body, intercoupling means are formed in the body adjacent each of said circuits, and connected to said circuits. A plurality of conductive paths are formed between said intercoupling means and carried by the body. Each intercoupling means includes a plurality of semiconductor regions formed in the semiconductor body, said regions in combination capable of assuming a first low impedance condition and a second high impedance condition to thereby selectively couple each of said circuits to selected conductive paths or decouple each of said circuits from said conductive paths. In a specific embodiment of the invention a massive monolithic integrated circuit is configured using intercoupling means in combination with small scale random access memory semiconductor circuits. A static MOS random access memory having a 2,048 word capacity, with 9 bits/word and an 11 bit address is provided.

Method of configuring an integrated circuit

A semiconductor structure, and method for fabrication, including a semiconductor body of one conductivity type having a major surface. A layer of opposite conductivity material is formed on said surface, said layer having an upper planar surface generally parallel to said major surface. Spaced first and second collector regions are carried by said layer. A third one conductivity region is formed in said layer spaced from said first and second region and extending to an exposed surface of said layer. A fourth region of opposite conductivity type is formed within said third region and extends to an exposed surface of said layer. The layer, third and forth regions form the respective regions of an opposite conductivity--one conductivity--opposite conductivity type source transistor. Additionally, the body, the layer and the first and second regions form the respective regions of a one conductivity--opposite conductivity--one conductivity switching transistor wherein said first and second regions form multiple collectors.

Integrated injection logic (I-squared L) with double-diffused type

Logic circuitry provides predetermined logic outputs in response to logical combinations of inputs. The circuitry includes a plurality of input devices for receiving logic inputs and capable of assuming conduction states in response to the logic levels of said inputs. At least one output device is connected to two or more input devices. Means having predetermined logic levels is provided connected intermediate the input and output devices for controlling the conduction state of the output devices as a function of the input devices and the predetermined logic levels.

Multivalued integrated injection logic circuitry and method

In an integrated circuit, a semiconductor body having a surface, spaced semiconductor circuits formed in the body, intercoupling means formed in the body adjacent each of said circuits, and connected to said circuits. A plurality of conductive paths are formed between said intercoupling means and carried by the body. Each intercoupling means includes a plurality of semiconductor regions formed in the semiconductor body, said regions in combination capable of assuming a first low impedance condition and a second high impedance condition to thereby selectively couple each of said circuits to selected conductive paths or decouple each of said circuits from said conductive paths. In a specific embodiment of the invention a massive monolithic integrated circuit is configured using intercoupling means in combination with small scale random access memory semiconductor circuits. A static MOS random access memory having a 2,048 word capacity, with 9 bits/word and an 11 bit address is provided.

Massive monolithic integrated circuit

A high density semiconductor structure and method is disclosed including a semiconductor body of one conductivity having a substantially planar surface. A first region of one conductivity is formed in the body and extends to the surface. A layer of opposite conductivity is interposed between the first region and the body said layer having relatively thin and uniform walls which extend to separate the first region from the body. At least one opposite conductivity region is formed entirely within the first region and extends to the surface. An opposite conductivity region is formed in the body and overlaps a portion of the layer. Lead means are provided for contacting each of the respctive regions and the body. The collector-up injection logic structure thus formed requires little or no surface area for the injection source transistor.

High density collector-up structure

Unidirectional and bidirectional bipolar logic transmission gates have an input, an output, a gate control, supply and common terminals. The unilateral transmission gate circuit includes first and second switching transistors and associated first and second source tranisistors. The transistors each have collector, base and emitter electrodes, said first source transistor emitter being connected to said supply terminal. The collector of the first switching transistor is connected to the base of the second switching transistor and defines a gate logic node. The base of the first switching transistor is connected to the first input terminal and the collector of the second switching transistor is connected to the output terminal with both switching transistor emitters being connected to the common terminal. Gate switching means is connected between said gate logic node and said gate control input, said means being responsive to first and second logic levels at said gate control input for driving said gate logic node to first and second states causing the transmission gate to assume open and closed states from input to output. A bidirectional bipolar logic transmission gate includes an additional gate logic node and gate switching means simultaneously drives said gate logic node and additional gate logic node to first and second states causing the transmission gate to assume bilateral open and closed states between said first and second input and output terminals.

Collector-up logic transmission gates

In a semiconductor structure, a semiconductor body of one conductivity type having a planar surface and a first region of opposite conductivity formed in said body and extending to said surface. Spaced second, third and fourth regions of one conductivity type are formed in said first region and extend to said surface. Fifth and sixth regions of opposite conductivity are respectively formed entirely within said second and third regions and extend to said surface. In addition a seventh region of one conductivity type may be formed spaced from said second, third and fourth regions and an eighth region of opposite conductivity type formed entirely within said seventh region. A method for forming the semiconductor logic structure is also disclosed.

Triple diffused logic elements

A decode driver useful in decoders for memory circuits. A plurality of transistors are connected in series between a first reference potential terminal and an output terminal. A second plurality of transistors are connected in parallel between a second reference potential terminal and the output terminal. Each of the transistors receives an input which functions to turn the transistors either on or off. The coding of the inputs determines whether the transistors to which the respective inputs are connected are turned on or off which in turn controls whether or not the output terminal is coupled to the first reference potential terminal or the second reference potential terminal.

Pseudo-complementary decode driver

An integrated circuit and method for forming the same including a lateral bipolar transistor having an increased current gain. Floating islands are formed in the emitter of the lateral transistor to have a conductivity type opposite that of the emitter and which act to channel current towards the periphery of the emitter, thereby directing the current towards the collector region. In addition, the integrated circuit includes a buried layer underlying the lateral transistor with the buried layer pinched very thin along a region which outlines the edge of the emitter for enhancing lateral current flow.

Lateral bipolar transistor for integrated circuits and method for

A semiconductor memory cell, and a method for fabrication, including a one conductivity semiconductor body having a major surface and an opposite conductivity layer formed on said major surface said layer having a planar surface. Means extend from said planar surface through said layer to contact said body for isolating portions of said layer into first and second device regions. First and second device regions each include a one conductivity region formed in said device region extending to said planar surface, an opposite conductivity region formed within said one conductivity regions extending to said surface, and a metal-to-semiconductor contact carried by said device region at said planar surface. Lead means include means for ohmic interconnection of opposite conductivity regions formed in said first and second device regions, means for interconnecting said first device region and said one conductivity region formed in said second device region. Lead means further includes means for interconnection of said second device region and said one conductivity region formed in said first device region. Additional lead means is provided for coupling said metal-to-semiconductor contacts, said semiconductor body and said interconnected opposite conductivity regions with external circuitry.

Cross coupled semiconductor memory cell

A collector-up binary structure of the type having spaced semiconductor regions forming a plurality of active devices for interconnection as a binary circuit is disclosed. The structure includes a semiconductor body of one conductivity having a planar surface, and spaced first, second, third and fourth transistors formed in said body. Fifth, sixth, seventh and eighth transistors are included, said fifth and sixth transistors being formed in the base regions of said second transistor and said seventh and eighth transistors being formed in the base region of said fourth transistor. Lead means provides ohmic contact to each of the respective regions of the respective transistors and interconnecting means is provided for connecting the plurality of active devices as a binary circuit. A structure further including ninth and tenth source transistors is also disclosed.

Collector-up semiconductor circuit structure for binary logic

A high speed threshold switching integrated circuit including a transistor and an integrally formed tunnel diode connected in parallel between the base and emitter of the transistor. The heavy doping necessary for the tunnel diode is achieved through the use of ion implantation. A current pulse applied to the emitter-base contact of the integrated circuit causes no collector current to flow until the point at which the rising current pulse exceeds the peak current of the tunnel diode. As the tunnel diode goes into the negative resistance region the transistor is turned on and rapidly pushed into near saturation with a consequent rapidly rising collector current.

Threshold switching integrated circuit and method for forming the same

A bipolar collector-up dynamic memory cell of the type utilized for storing information by writing and alternately reading information on a word line in response to a bit signal input. The memory cell includes a semiconductor body of one conductivity type having a planar surface, and a first transistor formed in the body having emitter, base and collector regions. The emitter is coupled to the word line and the base is coupled to the bit signal input. The collector region is of opposite conductivity type and is formed in the body extending to the surface to form a junction boundary between the collector and the body capable of exhibiting capacitance thereacross. A second transistor is formed in the body having emitter, base and collector regions. The base region is coupled to the bit signal input. The emitter and collector regions are connected between the word line and the collector of the first transistor and are capable of providing a forward current path from said first transistor collector to the word line. Means is also disclosed for writing and reading logic one and zero information bits in the memory cell.

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San Jose, CA, United States of America

Lewis K Russell