Motorola Corporation

Other

Lewis E Terry

Stephen P Robb

Bertrand Francis Cambou

Francine Y Robb

Israel A Lesk

William C Dunn

Raymond Mervin Roop

Ljubisa Ristic

Gary V Fay

John P Phipps

Judith L Sutor

Judy L Sutor

Pern Shaw

Yee-Chaung See

Frank S d'Aragona

Robert E Rutter

Craig A Cavins

Floyd E Anderson

Frank T Secco d'Aragona

Emily M Thompson

A method of fabricating an integrated circuit (272) having memory, logic, high voltage, and high current functionality uses a modular implant process step (104) to form a drain extension region (204), a source extension region (205), and a base extension region (206) in a substrate (200). The dopants from the modular implant process step (104) are later diffused into the substrate (200) during a LOCOS process step (105). A modular gate oxide formation step (111) produces three different thicknesses of gate oxides (309, 311, 312) which provide ultra high voltage, high voltage, and low voltage functionality for the integrated circuit (272).

Method of fabricating an EPROM with high voltage transistors

A semiconductor device having an improved protection scheme and a temperature compensated sustaining voltage is provided by integrating a plurality of temperature compensated voltage reference diodes between the drain and the gate of the semiconductor device. The diodes protect the device by clamping the device's sustaining voltage to the total avalanche voltage of the diode. The device will dissipate any excessive energy in the conduction mode rather than in the more stressful avalanche mode. In addition, the plurality of diodes will provide for a temperature compensated sustaining voltage of the semiconductor device. The plurality of diodes are formed back-to-back in polysilicon. The positive temperature coefficient of the avalanching junction of each diode pair is compensated for by the negative temperature coefficient of the forward biased junction.

Method for making semiconductor device having high energy sustaining

A plurality of doped areas (12, 13, 14) are formed on a surface of a semiconductor wafer. A titanium nitride layer (17) is used for covering the plurality of doped areas (12, 13, 14) and for providing electrical connection between the doped areas (12, 13, 14). The titanium nitride layer (17) substantially prevents dopants from diffusing into the titanium nitride (17) and subsequently counterdoping the doped areas (12, 13, 14) during subsequent high temperature processing operations.

Method of forming a conductive diffusion barrier

An environmental sensor integrated with high current drive device is provided. An environmental sensor is fabricated on a semiconductor substrate using conventional MOS process used for N-well CMOS logic and DMOS power transistors. An N-well is preferably used as a junction etch stop for micromachining of mechanical sensor components. A high voltage P-type region is used to electrically isolate the high current device from the sensor device. By locating the sensor device away from the high current drive device on a common semiconductor substrate, good performance can be achieved from the sensor even while the high current device dissipates a large amount of power.

Integrated circuit for sensing an environmental condition and producing

A plurality of doped areas (12, 13, 14) are formed on a surface of a semiconductor wafer. A titanium nitride layer (17) is used for covering the plurality of doped areas (12, 13, 14) and for providing electrical connection between the doped areas (12, 13, 14). The titanium nitride layer (17) substantially prevents dopants from diffusing into the titanium nitride ( 17 ) and subsequently counterdoping the doped areas (12, 13, 14) during subsequent high temperature processing operations.

Conductive diffusion barrier of titanium nitride in ohmic contact with a

Semiconductor device having high energy sustaining capability and a

A microprocessor having a monolithically integrated environmental sensor is provided. The microprocessor is shielded from an environmental signal by isolation which is specific to the type of sensor used, thereby allowing the sensor to be exposed to the environmental signal. Optionally, high current drive circuitry is integrated with the microprocessor-sensor circuit to provide a monolithic device which allows control of power loads based in part on output from an environmental sensing device.

Microprocessor having environmental sensing capability

An insulated gate bipolar device is formed on a multiple conductivity substrate. The multiple conductivity substrate comprises interspersed regions of N+ and P+ semiconductor material. In a preferred embodiment, the N+ and P+ regions are arranged in a checkerboard, mosaic pattern on a bottom side of the substrate. The P+ region serves to conductivity modulate an N epitaxial layer in which the IGBT structure is formed while the N+ regions improve low current conductivity, reduce minority carrier recombination time, and make an integral drain source diode accessible from the drain and source electrodes.

Method of making enhanced insulated gate bipolar transistor

MOSFET devices or circuits incorporating an improved substrate temperature sensing element are obtained by forming a PN junction directly on a thin (gate) dielectric region. The temperature sense junction is desirably formed in a poly layer. By mounting it directly on thin (gate) dielectric its thermal response to temperature changes in the substrate is improved while still being electrically isolated from the substrate. It is desirable to provide over-voltage protection elements coupled to the junction to avoid rupture of the underlying thin dielectric. Because the sense diode and all the over-voltage protection devices may be made of poly with junctions perpendicular to the substrate, the structure is particularly compact and simple to fabricate.

Process for forming a semiconductor structure with closely coupled

Semiconductor structure with closely coupled substrate temperature sense

An integrated circuit having a microprocessor core interfaced to large power transistors is described. This integrated circuit provides the capability to intelligently control and drive loads requiring currents exceeding 250 milli amps. The large power transistors are built in a technology compatible with the microprocessor core technology resulting in a more readily manufacturable circuit. The microprocessor core is layed out in a manner which provides the greatest distance between the most heat sensitive microprocessor core circuits and the power devices. On chip temperature sensing and feedback is provided for junction temperature monitoring and control.

Microprocessor having high current drive

A vertical field effect transistor is provided which has its sources arranged in a pattern to essentially eliminate inactive common drain area between the sources. The preferred arrangement is to use rectangular source areas to form columns and rows in the arrangement. Every other row is shifted so that a source in a shifted row is positioned between sources in an adjacent row. The rows are then spaced closer together thereby achieving the substantial elimination of inactive drain area. The elimination of inactive drain area results in low on resistance during the conductive state of the vertical field effect transistor.

FET structure arrangement having low on resistance

An improved MOS transistor and method for making that transistor are provided. The improved transistor is characterized by decreased size, improved switching speed, and improved reliability in inductive load use. The improved structure is achieved through the use of a low minority carrier injecting source region formed, for example, by providing a low barrier height metal silicide. The metal silicide source provides a source of majority carriers but little minority carrier injection and hence little parasitic bipolar transistor action.

Growing community of inventors

Phoenix, AZ, United States of America

Lewis E Terry