Synopsys, Inc.

Nokia Corporation

Synplicity, Inc.

Levent Oktem

Kenneth S McElvain

Mustafa Ispir

Tolga Capin

A method and apparatus to design a circuit is described. In on embodiment, the method comprises selecting a target clock for a design of the circuit, and determining a plurality of latencies for a portion of the circuit. The method further comprises determining a representation of a data flow graph for the portion of the circuit, the data flow graph having a first node connected with a second node by a number of extra delays determined based on the target clock and the plurality of latencies, the first node and second node representing paths that start from and end in registers in the portion of the circuit, the first node connecting to a node between a first input of the portion of the circuit and an input of a register of the portion of the circuit. The method continues to retime the design for the circuit to operate at the target clock based on the representation of the data flow graph, wherein at least one of the selecting, determining, and retiming is performed by a processor.

Circuit design and retiming

A method for designing an integrated circuit is described. The method comprises converting behavioral descriptions of the integrated circuit to register transfer level (RTL) descriptions. The method comprises at least one of the behavioral descriptions including frame synthesis with an input frame and a corresponding output frame. In one embodiment, the method further comprises providing at least two solutions for performing partial and complete operations for simulations as hardware component combinations, associating each solution with a cost, and selecting the solution with the lowest cost as the hardware component combination for a final design of the integrated circuit.

Using entropy in an colony optimization circuit design from high level synthesis

Methods and apparatuses to hierarchically retime a circuit. In at least one embodiment of the present invention, a module of a circuit is designed with a plurality of different latencies to have a plurality of different minimum clock periods (e.g., through retiming at the module level). In one example, the minimum clock periods are determined from detailed timing analyses after the placement and routing for the module; and, in retiming the circuit that contains the module, a data flow graph representation of the module is constructed based on the target clock period of the circuit and the correlation between the latencies and the minimum clock periods. In at least one embodiment of the present invention, hierarchical retiming is performed in which portions of the circuit is retimed to generate results (e.g., for different latencies), which are selectively used for the retiming of the entire circuit based on the target clock period.

Methods and apparatuses to time-share resources having internal states are described. A first design of a system having a plurality of instances of a logical block to perform logical operations is received. The instances may have internal states. The system is automatically transformed to generate a second design having a fewer quantity of time-shared instances of the logical block. The plurality of the instances in the first design is replaced with the fewer time-shared instances in the second design. The time-shared instances in the second design have elements to time multiplex the internal states.

Automated synthesis of multi-channel circuits

Methods and apparatuses for retiming of multirate system for clock period minimization with a polynomial time without sub-optimality. In an embodiment, a normalized factor vector for the nodes of multirate graph is introduced, allowing the formulation of the multirate graph retiming constraints to a form similar to a single rate graph. In an aspect, the retiming constraints are formulated to allowed the usage of linear programming methodology instead of integer linear programming, thus significantly reducing the complexity of the solving algorithm. The present methodology also uses multirate constraints, avoiding unfolding to single rate equivalent, thus avoiding graph size increase. In a preferred embodiment, the parameters of the multirate system are normalized to the normalized factor vector, providing efficient algorithm in term of computational time and memory usage, without any sub-optimality.

Retiming of multirate system

A method and apparatus for using entropy in ant colony optimization circuit design from high level synthesis is described. In one example, an operation to be performed by a circuit is selected. A plurality of hardware components for performing the operation are represented with a data flow graph having edges and nodes. A plurality of solutions for performing the operation are simulated as hardware component combinations represented as paths on the data flow graph. For each solution the cost including a number of edges and nodes traversed on the data flow graph and a supplemental sub-integer cost is determined and a solution is selected with the lowest cost as a hardware component combination for a circuit.

Method and apparatus for using entropy in ant colony optimization circuit design from high level synthesis

Methods and apparatuses to automatically generate time multiplexed multi-channel circuits from single-channel circuits. At least one embodiment of the present invention automatically and efficiently synthesize multi-channel hardware for time-multiplexed resource sharing by automatically generating a time multiplexed design of multi-channel circuits from the design of a single-channel circuit. Channel specific elements of the single-channel design (e.g., registers and memories) are replaced with corresponding elements of N-times more capacity for pipelining the signal processing for multiple channels.

Method and apparatus for automated synthesis of multi-channel circuits

Method and apparatus for circuit design and retiming

A method and corresponding apparatus for selecting a sequence of quantization parameter values in a video encoder, the video encoder being arranged to encode a video frame as a sequence of n macroblocks and to assign a quantization parameter value for each macroblock of the video frame. The method includes steps ( ) in which quantization parameter values assigned to at least a subset of said sequence of n macroblocks are optimized in such a way as to minimize a cost associated with their encoding.

Method and apparatus for selecting macroblock quantization parameters in a video encoder

Apparatus, and an associated method, for facilitating communication of a vector graphic representation, or other content, pursuant to effectuation of a communication service. The content forms, for instance, an animated graphic, such as that used in a mobile communication application to effectuate an animated multi-media message. The vector graphic is encoded according to codewords that function to compress the data prior to its communication upon a radio link. And, once delivered to a receiving station, a decoder decodes the content into unencoded form. Codebooks are utilized and accessed by an encoder and decoder of a sending/receiving station pair.

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Sunnyvale, CA, United States of America

Levent Oktem