Other

The University of Akron

Supercon, L.l.c.

Lev Raphaelovich Freydel

Nathan Ida

Abdullah A Abonamah

A redundant computer system utilizing comparison diagnostics and voting techniques includes a plurality of redundant channels. Each pair of the processors receives/obtains process information from I/O modules via dual redundant sensors (DRS). The processors execute an application program, whereby output module is utilized for comparing output data of the two processors. Output module receives output data from neighboring modules, if there is a deviation or other disparity in the output data. Each pair of processors, a voter and an improper sequence detector component disables the output module, if a majority of signals vote that output module fails. In addition, the system uses 2-of-3 voting, the system remains operational in the presence of up two transient or hard failures.

Redundant computer system utilizing comparison diagnostics and voting techniques

A multiple redundant computer system includes three primary processor modules (PPM) and three redundant processor modules (RPM) operating synchronously. Primary and redundant processor modules are dissimilar in hardware and software for decreasing the probability of a common cause system failure. Each primary and redundant processor module receives input data from associated primary and redundant input modules respectively, executes control program and transfers output data to an output module. The output module produces a system output as the result of 2-out-of-3 voting among output data generated by PPMs. In response to PPMs hard failures, the output module still produces the system output as the result of 2-out-of-3 voting among output data generated by any combination of the PPM and the RPM. As such, the system is able to operate properly even though five-out-of six processor modules have failed. The output module also compares output data that it has received from each pair of the associated PPM and RPM for detecting a disparity between said output data due to the occurrence of transient faults. Additionally, the output module produces the system output as the result of 2-out-of-2 and 1-out-of-1 voting upon the occurrence of disparity of output data generated by the associated PPM and RPM in one and two pairs of the associated PPM and RPM respectively.

Multiple redundant computer system combining fault diagnostics and majority voting with dissimilar redundancy technology

A dual/triple redundant computer system having in one of the preferred embodiments triple redundant I/O modules and dual redundant central processor modules (CPM) that operate in parallel executing the same application program. Each input module includes three input circuits operating in parallel. The first CPM receives input data from first and third input circuits and transmits input data of the first input circuit to the second CPM. The second CPM receives input data from second and third input circuits and transmits input data of the second input circuit to the first CPM. Each CPM then performs a two-out-of-two vote among input data produced by first, second, and third input circuits and utilizes an outvoted data as input to the application program to provide output data by execution of the application program. Each output module includes three microcontrollers operating in parallel. First and second microcontroller receives output data respectively from first and second CPM, while a third microcontroller receives at the same time output data from both first and second CPM. First microcontroller transmits output data to a first and a second output circuit. Second microcontroller transmits output data to second and third output circuit. The third microcontroller performs a selected logic operation among output data produced by first and second CPM and then transmits a result of this operation to third and first output circuits. Each output circuit generates a logical product of output data received from two associated microcontrollers. Outputs of first, second, and third output circuit are connected to each other for providing a two-out-of-three voting among output data produced by first, second, and third microcontroller, and for allowing the system to generate a system output as a result of a two-out-of-two voting of output data generated by first and second central processor modules.

Dual/triple redundant computer system

A hybrid multiple redundant computer system having redundant input modules, central processor modules, and output modules operating in parallel, where output circuits within each output module are connected to associated microcontrollers, such that, a first output circuit is connected to a first and a third microcontroller, a second output circuit is connected to a second and the first microcontroller, and a third output circuit is connected to the third and the second microcontroller; each output module further comprising watchdog controllers for detecting faults within the microcontrollers or central processing modules, where the watchdog controllers produce alarm signals upon detection of a failure within these components; the output circuits further including means for providing a 2-of-3 vote among data produced by three central processor modules if alarm signals are not activated and for reverting to a 2-of-2 and 1-of-1 vote in the presence of one and two faulty components respectively. The microcontrollers further including fault diagnostic and fault recovering means to provide correct system outputs in the presence of up to at least two faulty components in the output circuits.

Hybrid triple redundant computer system

A hybrid multiple redundant computer system ( ) having at least three parallel operating processing units ( ) including input module ( ), central processor module ( ), and output module ( ) in each processing unit is disclosed. The central processor module ( ) is connected to the associated input module ( ) and connected to primary and secondary output circuits ( ) located in the associated output module ( ) and in the neighboring output module ( ) respectively. Each processing unit ( ) further includes a watchdog controller ( ) that monitors the associated central processor module ( ) and transfers an alarm signal ( ) to each output module ( ) in the event that a central processor module ( ) fails. Primary and secondary output circuits ( ) in each output module ( ) control an output voter network ( ) and perform selectable but different logical functions among output data of the respective central processor modules ( ) and alarm signals ( ) for providing no single point of failure within the output module ( ). If alarm signals ( ) are not activated, the system generates an output ( ) using two-of-three vote among output data produced by three central processor modules ( ). In the event that one or two central processor modules ( ) fail, the system is reconfigured to a two-of-two and to a one-of-one vote configuration respectively. Each central processor module ( ) in turn monitors the status of all of the system components and disables faulty outputs by opening a fault recovery switch ( ) in the respective output module ( ) allowing continued system operation in the face of as many as two faults within any system components.

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Akron, OH, United States of America

Lev Raphaelovich Freydel