Intel Corporation

Lev Makovsky

Alexander Gendler

Igor Yanover

Gavri Berger

Zeev Sperber

Efraim Rotem

Stanislav Shwartsman

Arkady Bramnik

Haim Granot

Elkana Korem

Daniela Kaufman

Hanan Shomroni

Edo Hachamo

Raanan Sade

Ron Gabor

Nir Rosenzweig

Michael Mishaeli

Lihu Rappoport

Adi Yoaz

Ofer Levy

Julius Yuli Mandelblat

Larisa Novakovsky

Alexander Lyakhov

George Leifman

Ariel Sabba

Niv Tokman

Tomer Weiner

In an embodiment, a processor includes processing cores to execute instructions; and throttling logic. The throttling logic is to: determine an average capacitance score for execution events in a sliding window; perform frequency throttling when the average capacitance score exceeds a throttling threshold; determine a count of frequency throttling instances; and in response to a determination that the count of frequency throttling instances exceeds a maximum throttling value, increase the throttling threshold and concurrently reduce a baseline frequency. Other embodiments are described and claimed.

Adjusting a throttling threshold in a processor

In one embodiment, a processor core has one or more execution units, a first memory array having a first protection circuit to provide soft error protection to the first memory array, and a control circuit. A power controller coupled to the core may include a protection control circuit, in response to an update to an operating voltage to be provided to the core, to cause the core to disable the first protection circuit. Other embodiments are described and claimed.

System, apparatus and method for dynamically controlling error protection features of a processor

A processor of an aspect includes a decode unit to decode a thread pause instruction from a first thread. A back-end portion of the processor is coupled with the decode unit. The back-end portion of the processor, in response to the thread pause instruction, is to pause processing of subsequent instructions of the first thread for execution. The subsequent instructions occur after the thread pause instruction in program order. The back-end portion, in response to the thread pause instruction, is also to keep at least a majority of the back-end portion of the processor, empty of instructions of the first thread, except for the thread pause instruction, for a predetermined period of time. The majority may include a plurality of execution units and an instruction queue unit.

Thread pause processors, methods, systems, and instructions

In an embodiment, a processor includes a core to execute instructions, where the core includes a clock generation logic to receive and distribute a first clock signal to a plurality of units of the core, a restriction logic to receive a restriction command and to reduce delivery of the first clock signal to at least one of the plurality of units. The restriction logic may cause the first clock signal to be distributed to the plurality of units at a lower frequency than a frequency of the first clock signal. Other embodiments are described and claimed.

Restricting clock signal delivery in a processor

In an embodiment, a processor includes at least a first core. The first core includes execution logic to execute operations, and a first event counter to determine a first event count associated with events of a first type that have occurred since a start of a first defined interval. The first core also includes a second event counter to determine a second event count associated with events of a second type that have occurred since the start of the first defined interval, and stall logic to stall execution of operations including at least first operations associated with events of the first type, until the first defined interval is expired responsive to the first event count exceeding a first combination threshold concurrently with the second event count exceeding a second combination threshold. Other embodiments are described and claimed.

Method and apparatus to protect a processor against excessive power usage

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Haifa, Israel

Lev Makovsky