National Semiconductor Corporation

Marvell Israel (misl) Ltd.

Lev Epstein

Gideon Intrater

Moshe Doron

Israel Greiss

Amos Intrater

Yachin Afek

Oved Oz

Meir Tsadik

Omri Viner

Iddo Carmon

Alberto Sandbank

Ronny Cohen

Zvi Greenfeld

Yehezkel Tzadik

Itael Fraenkel

Lior Katzri

Raya Levitan

Maurice Valentaten

Ilan Shimony

Andy Birenbaum

Sidi Yomtov

Eitan E Rosen

Aspects of the disclosure provide an integrated circuit and method for varying a frequency of a clock signal to accommodate critical paths in the integrated circuit. The integrated circuit can include a clock generator configured to generate a clock signal having a clock frequency that is variable, circuitry that includes a plurality of critical modules that can be selectively activated to operate under control of the clock signal, each critical module including one or more critical paths that a default clock frequency cannot accommodate, and a controller that causes the clock generator to vary the clock frequency of the clock signal based on propagation delays of those critical paths in activated critical modules.

Critical paths accommodation with frequency variable clock generator

An integrated data processing platform for processing a digital signal that includes a general purpose processor and a digital signal processor (DSP) module. The DSP module recovers digital data from a digital signal utilizing a sequence of DSP operations selected by the general purpose processor. The general purpose processor processes the digital data recovered by the DSP module, but is also available to perform general purpose tasks. A shared internal memory array selectively provides information to the DSP module and to the general purpose processor. The information stored in the internal memory array includes operands utilized in the execution of the DSP algorithm and selected instructions and data utilized by the general purpose CPU either for controlling the execution of the DSP algorithm or for executing its own general purpose tasks. While in many applications the data processing system will include an analog front end that converts a modulated input signal received on an analog transmission channel to a corresponding digital signal for processing by the data processing system, the data processing system may also receive the digital signal directly from a digital source.

Integrated digital signal processor/general purpose CPU with shared internal memory

Integrated digital signal processor/general purpose CPU with shared

An integrated circuit structure, having a central processing unit (CPU) formed as a part thereof, for configuring the CPU for operating in an operating mode selected from a plurality of possible operating modes. The possible operating modes include a first possible operating mode that operates exclusively on internal memory storage elements, a second possible operating mode that operates exclusively on external memory storage elements via an external bus connected to a first portion of a plurality of general purpose I/O pins, and a third possible operating mode that operates on external memory storage elements via an external bus connected to a second portion of the general purpose I/O pins such that additional external I/O circuitry is necessary to handle I/O transfers.

Integrated data processing system including CPU core and parallel,

An integrated data processing system includes a shared internal bus for transferring both instructions and data. A shared bus interface unit is connected to the shared internal bus and connectable via a shared external bus to a shared external memory array such that instructions and data held in the shared external memory array are transferrable to the shared internal bus via the shared bus interface unit. A general purpose (GP) central processing unit (CPU) is connected to the shared internal bus for retrieving GP instructions. The GP CPU includes an execution unit for executing GP instructions to process data retrieved by the GP CPU from the shared internal bus. A digital signal processor (DSP) module connected to the shared internal bus, the DSP module includes a signal processor for processing an externally-provided digital signal received by the DSP module by executing DSP command-list instructions. Execution of DSP command-list code instructions by the DSP module is independent of and in parallel with execution of GP instructions by the GP CPU. A shared internal memory that holds command-list code instructions and is connected for access by the DSP module for retrieval of command-list code instructions for execution by the DSP module and for access by the GP CPU for storage and retrieval of instructions and data.

An integrated data processing system includes a shared internal bus for transferring both instructions and data. A shared bus interface unit is connected to the shared internal bus and connectable via a shared external bus to a shared external memory array such that instructions and data held in the shared external memory array are transferrable to the shared internal bus via the shared bus interface unit. A general purpose (GP) central processing unit (CPU) is connected to the shared internal bus for retrieving GP instructions. The OP CPU includes an execution unit for executing GP instructions to process data retrieved by the GP CPU from the shared internal bus. A digital signal processor (DSP) module connected to the shared internal bus, the DSP module includes a signal processor for processing an externally-provided digital signal received by the DSP module by executing DSP command-list instructions. Execution of DSP command-list code instructions by the DSP module is independent of and in parallel with execution of GP instructions by the GP CPU. A shared internal memory that holds command-list code instructions and is connected for access by the DSP module for retrieval of command-list code instructions for execution by the DSP module and for access by the GP CPU for storage and retrieval of instructions and data.

Integrated CPU core and parallel, independently operating DSP module and

Growing community of inventors

Holon, Israel

Lev Epstein