Altasens, Inc.

Rockwell Science Center, Inc.

Ess Technology, Inc.

Pictos Technologies, Inc.

Innovative Technology Licensing LLC

Rockwell International Corporation

Obsidian Sensors, Inc.

Other

Jvc Kenwood Corporation

Lester Joseph Kozlowski

David Lawrence Standley

William E Tennant

Richard Arthur Mann

William A Kleinhans

Giuseppe Rossi

Gerard Sullivan

Anders Kongstad Petersen

Roger E DeWames

Ilya Koshkin

Brian T McDermott

Jeffrey Alan McKee

Gregory Chow

Laurent Blanquart

John Richardson

Henry C Lin

Markus Loose

Gaurang Patel

Ying Huang

Qianjiang Mao

Frank Chang

Alfredo Tomasini

Wu-Jing Ho

A low-power image sensor includes a plurality of light-sensitive pixel cells, a plurality of analog-to-digital converters (ADCs) and image processing circuitry. The image sensor can be disposed in multiple semiconductor layers such that the pixel cells are disposed in a first layer and various other components are disposed in the second layer or between the first layer and the second layer. The image sensor is configured such that the analog output of a pixel cell is sampled by a first ADC and a second ADC within respective first and second dynamic ranges, the second dynamic range being greater than the first dynamic range. The first ADC and the second ADC sample the analog output with different sampling resolutions. The digital outputs of the first ADC and the second ADC are subsequently used by an image processor to generate a pixel value for an image frame.

Systems and methods for low-power image digitization

Various technologies described herein pertain to combining high dynamic range techniques to enable rendering higher dynamic range scenes with an image sensor. The image sensor can implement a combination of spatial exposure multiplexing and temporal exposure multiplexing, for example. By way of another example, the image sensor can implement a combination of spatial exposure multiplexing and dual gain operation. Pursuant to another example, the image sensor can implement a combination of temporal exposure multiplexing and dual gain operation. In accordance with yet another example, the image sensor can implement a combination of spatial exposure multiplexing, temporal exposure multiplexing, and dual gain operation. The image sensor can be formed on a single wafer or the image sensor can be a 3D-IC image sensor that includes at least two vertically integrated layers.

Image sensor combining high dynamic range techniques

Various technologies described herein pertain to combining high dynamic range techniques to enable rendering higher dynamic range scenes with an image sensor. The image sensor can implement a combination of spatial exposure multiplexing and temporal exposure multiplexing, for example. By way of another example, the image sensor can implement a combination of spatial exposure multiplexing and dual gain operation. Pursuant to another example, the image sensor can implement a combination of temporal exposure multiplexing and dual gain operation. In accordance with yet another example, the image sensor can implement a combination of spatial exposure multiplexing, temporal exposure multiplexing, and dual gain operation.

An image sensor having global shutter circuitry and an extremely fine pixel pitch. Disclosed image sensors combine global shutter circuitry with rolling shutter circuitry for respective subsets of sensor pixels to marry imaging benefits of global shutter circuitry with relatively small circuit overhead of rolling shutter circuitry. Such image sensors can achieve improved optical performance with smaller pixel pitch and optical resolution than existing global shutter image sensors.

Global shutter image sensor having extremely fine pitch

An image sensor architecture provides an SNR in excess of 100 dB, without requiring the use of a mechanical shutter. The circuit components for an active pixel sensor array are separated and arranged vertically in at least two different layers in a hybrid chip structure. The top layer is preferably manufactured using a low-noise PMOS manufacturing process, and includes the photodiode and amplifier circuitry for each pixel. A bottom layer is preferably manufactured using a standard CMOS process, and includes the NMOS pixel circuit components and any digital circuitry required for signal processing. By forming the top layer in a PMOS process optimized for forming low-noise pixels, the pixel performance can be greatly improved, compared to using CMOS. In addition, since the digital circuitry is now separated from the imaging circuitry, it can be formed using a standard CMOS process, which has been optimized for circuit speed and manufacturing cost. By combining the two layers into a stacked structure, the top layer (and any intermediate layer(s)) acts to optically shield the lower layer, thereby allowing charge to be stored and shielded without the need for a mechanical shutter.

Image sensor with hybrid heterostructure

An image sensor architecture for an active pixel sensor array are separated and arranged vertically in at least two different layers in a hybrid chip structure. The top layer includes the photodiode and amplifier circuitry for each pixel. A bottom includes the pixel circuit components and any digital circuitry required for signal processing. By forming the top layer in a process optimized for forming low-noise pixels, the pixel performance can be greatly improved. In addition, since the digital circuitry is now separated from the imaging circuitry, it can be formed using a process which has been optimized for circuit speed and manufacturing cost. By combining the two layers into a stacked structure, the top layer (and any intermediate layer(s)) acts to optically shield the lower layer, thereby allowing charge to be stored and shielded without the need for a mechanical shutter.

An image sensor architecture provides an SNR in excess of 100 dB, without requiring the use of a mechanical shutter. The circuit components for an active pixel sensor array are separated and arranged vertically in at least two different layers in a hybrid chip structure. The top layer is preferably manufactured using a low-noise PMOS manufacturing process, and includes the photodiode and amplifier circuitry for each pixel. A bottom layer is preferably manufactured using a standard CMOS process, and includes the NMOS pixel circuit components and any digital circuitry required for signal processing. By forming the top layer in a PMOS process to optimized for forming low-noise pixels, the pixel performance can be greatly improved, compared to using CMOS. In addition, since the digital circuitry is now separated from the imaging circuitry, it can be formed using a standard CMOS process, which has been optimized for circuit speed and manufacturing cost. By combining the two layers into a stacked structure, the top layer (and any intermediate layer(s)) acts to optically shield the lower layer, thereby allowing charge to be stored and shielded without the need for a mechanical shutter.

Systems and methods are provided that facilitate employing a plurality of independent reset buses for a column of pixels in a pixel array of a CMOS sensor imager. Utilization of the plurality of independent reset buses for the column of pixels can enable independent reset to be effectuated when employing sub-frame integration. For example, rows to be read and reset during a given readout time interval can be selected based upon one or more criteria. Further, each of the rows selected during the given readout time interval can be associated with a respective distinct reset bus. By leveraging the plurality of independent reset buses, uniformity in pixel operation can be maintained whether operating in full frame integration mode or sub-frame integration mode. Thus, noise resultant from changing between integration modes can be mitigated by using the plurality of independent reset buses.

Sub-frame tapered reset

A low-noise active pixel circuit is disclosed that efficiently suppresses reset (kTC) noise by using a compact preamplifier consisting of a photodetector and only three transistors of identical polarity, in conjunction with ancillary circuits located on an imager's periphery. The use of only three transistors with a tapered reset signal allows the optical area to be increased, while still providing a low-noise imager.

Compact active pixel with low-noise image formation

A color filter array (CFA) and image processing system wherein a color filter overlaying an image sensor has a luminance element (i.e. green filter in RGB space, or yellow in CMY space) that is made larger than the other two chrominance elements (i.e. red, blue or cyan, magenta). Additionally, overlaying micro-lenses may be sized to correspond to the relative sizes of the underlying color filters. The optimized filter array is compatible with existing de-mosaic image processing.

High sensitivity color filter array

A dual sensitivity image sensor provides a standard mode and a high-sensitivity mode of operation via iSoC integration. In addition to boosting sensitivity, the high sensitivity mode also reduces temporal noise thereby optimally boosting the Signal-to-Noise Ratio (SNR) of the image sensor. The circuit does not significantly increase pixel complexity and requires minimal changes to the support circuits in the iSoC including the addition of support and control circuitry to facilitate seamless mode change.

Dual sensitivity image sensor

An apparatus and method for forming optical black pixels having uniformly low dark current. Optical Black opacity is increased without having to increase Ti/TiN layer thickness. A hybrid approach is utilized combining a Ti/TiN OB layer in conjunction with in-pixel metal stubs that further occlude the focal radius of each pixel's incoming light beam. Additional metal layers can be used to increase the opacity into the infrared region.

Growing community of inventors

Simi Valley, CA, United States of America

Lester Joseph Kozlowski