Qualcomm Incorporated

International Business Machines Corporation

Xilinx, Inc.

Leslie Mark DeBruyne

Brian Stempel

James Norris Dieffenderfer

Michael Scott McIlvaine

Thomas Andrew Sartorius

Anthony Correale, Jr

Rodney Wayne Smith

Ahmad R Ansari

Stephen M Douglass

Daren Eugene Streett

Nigel G Herron

Nabil A Rizk

Kevin Allen Sapp

Kevin Charles Burke

Brian Michael Stempel

Nabil Amir Rizk

Systems and methods are disclosed for maintaining an instruction cache including extended cache lines and page attributes for main cache line portions of the extended cache lines and, at least for one or more predefined potential page-crossing instruction locations, additional page attributes for extra data portions of the corresponding extended cache lines. In addition, systems and methods are disclosed for processing page-crossing instructions fetched from an instruction cache having extended cache lines.

Method and apparatus for tracking extra data permissions in an instruction cache

An instruction in an instruction cache line having a first portion that is cacheable, a second portion that is from a page that is non-cacheable, and crosses a cache line is prevented from executing from the instruction cache. An attribute associated with the non-cacheable second portion is tracked separately from the attributes of the rest of the instructions in the cache line. If the page crossing instruction is reached for execution, the page crossing instruction and instructions following are flushed and a non-cacheable request is made to memory for at least the second portion. Once the second portion is received, the whole page crossing instruction is reconstructed from the first portion saved in the previous fetch group. The page crossing instruction or portion thereof is returned with the proper attribute for a non-cached fetched instruction and the reconstructed instruction can be executed without being cached.

Methods and apparatus for managing page crossing instructions with different cacheability

A processor is operative to execute two or more instruction sets, each in a different instruction set operating mode. As each instruction is executed, debug circuit comparison the current instruction set operating mode to a target instruction set operating mode sent by a programmer, and outputs an alert or indication in they match. The alert or indication may additionally be dependent upon the instruction address following within a predetermined target address range. The alert or indication may comprise a breakpoint signal that halts execution and/or it is output as an external signal of the processor. The instruction address at which the processor detects a match in the instruction set operating modes may additionally be output. Additionally or alternatively, the alert or indication may comprise starting or stopping a trace operation, causing an exception, or any other known debugger function.

Debug circuit comparing processor instruction set operating mode

Method and apparatus for generating a test program for a programmable logic device having an embedded processor. Predetermined code is obtained to exercise at least one speed limiting path identified. To the predetermined code is added wrapper code to provide the test program, the wrapper code in part for loading the predetermined code into cache of the embedded processor for testing the at least one speed limiting path of the embedded processor identified.

Speed verification of an embedded processor in a programmable logic device

Growing community of inventors

Cary, NC, United States of America

Leslie Mark DeBruyne