Newisys, Inc.

International Business Machines Corporation

Leslie James Record

Robert Gontarek

Timothy M Damron

William G Kulpa

Michael Edward Lyons

An electronic assembly is described which includes a printed circuit board, and a processor and a memory mounted on the printed circuit board. A routing channel is provided in the printed circuit board comprising a plurality of conductors interconnecting the processor and the memory. A regulator assembly includes a regulator for providing power to the processor, a first connector mounted on the printed circuit board adjacent a first edge of the routing channel, and a second connector mounted on the printed circuit board adjacent a second edge of the routing channel opposite the first edge. The first and second connectors are coupled to the regulator and facilitate distribution of the power to the processor. The regulator and the first and second connectors form a bridge across the routing channel.

Mounting power handling components on printed circuit boards near high density routing channels

A disk drive backplane is described which includes a connector for interfacing with a corresponding connector on each of a plurality of carrier types. A plurality of status indicator arrays is provided, each of which corresponds to at least one of the carrier types and is operable to transmit status information. Each of the arrays is positioned to interface with a corresponding status interface on the corresponding carrier type(s). Circuitry is provided which enables one of the status indicator arrays thereby configuring the backplane to interface with a particular one of the carrier types.

Disk drive backplane capable of supporting multiple disk drive carrier designs

A method and system are disclosed for managing multiple requests issued by a requester to a number of peripheral devices coupled to a peripheral bus within a data processing system. A request issued by the requestor which specifies a particular operation to be performed is transmitted to a selected peripheral device vice the peripheral bus. In response to performance of the particular operation by the selected peripheral device within a first predetermined time period, successful completion of the request is reported to the requestor. In response to a failure of the selected peripheral device to perform the particular operation within the first predetermined time period, access to the peripheral bus by the multiple requests is limited. Thereafter, in response to a failure of the selected peripheral device to perform the particular operation within a second predetermined time period, a request timeout error is reported to the requester. However, in response to performance of the particular operation by the selected peripheral device within the second predetermined time period, successful completion of the request is reported to the requester. Thus, utilizing the present invention, request timeout errors due to peripheral bus saturation are minimized.

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Round Rock, TX, United States of America

Leslie James Record