Nvidia Corporation

Nvdia Corporation

Leslie E Neft

Michael A Ogrinc

Duncan Andrew Riach

Tyvis Cheung

Wayne Douglas Young

Dat T Nguyen

David Matthew Stears

Jesse S Clayton

One embodiment of the present invention sets forth a technique for controlling mode switches in hardware. The resource manager includes an 'is mode possible' function that evaluates a given mode in conjunction with the limitations of the hardware to determine if the given mode is feasible. The display driver is configured to call this function to validate a proposed mode before generating commands specifying the state changes for the display heads. The display software interface hardware module within the GPU processes these commands and follows a standard sequence of steps to implement the mode switch. The steps may include interrupts to the resource manager to re-validate the proposed mode, again calling the 'is mode possible' function, or perform operations that are not yet supported in the hardware. Advantageously, controlling mode switches in hardware enables less error-prone, more efficient, and more discerning mode switches relative to controlling mode switches in software.

System and method for controlling mode switches in hardware

A system, method, and computer program product are provided for synchronizing stereo signals. In use, stereo signals are synchronized amongst a plurality of display devices utilizing hardware.

Hardware-based system, method, and computer program product for synchronizing stereo signals

One embodiment of the present invention sets forth a system for computing and error checking configuration parameters related to raster image generation within a graphics processing unit. Input parameters are validated by a hardware-based error checking engine. A hardware-based pre-calculation engine uses validated input parameters to compute additional private configuration parameters used by the raster image generation circuitry within a graphics processing unit.

Active raster composition and error checking in hardware

An isochronous processor includes a state register, a functional unit, a control module, and an activation unit. The state register includes an arm buffer and an active buffer. The functional unit performs a transformation operation on the data stream in response to an active value of the control parameter obtained from the active buffer. The control module updates the arm value of the control parameter in the arm buffer in response to control instructions. The activation unit detects a load event propagating with the data stream and transfers the parameter value from the arm buffer to the active buffer in response to the load event. During this transfer, the control module is inhibited from updating the arm buffer.

Isochronous pipelined processor with deterministic control

A system and method for enabling or disabling clocks to one or more portions of hardware circuitry, for example a display sub-system of a personal computer. A processor generates a command or data to a first circuit configured to perform a function based at least on the command or data. A clock generator selectively supplies clocks to the first circuit and a second circuit configured to perform a second function. A software interface circuit coupled to the processor and the clock generator autonomously determines based at least on the command or data whether the second circuit will perform the second function or be idle in an upcoming period and disables one or more of the clocks to the second circuit if the second circuit will be idle in the upcoming period.

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Mountain View, CA, United States of America

Leslie E Neft