Intel Corporation

Cirrus Logic Inc.

Leslie E Cline

Edward J Chejlava, Jr

Barnes Cooper

Kenneth C Curt

Eric C Samson

Xia Dai

Millind Mittal

Varghese George

David Wyatt

David I Poisner

Aditya Navale

Michael N Derr

John William Horigan

Frank P Hart

Ishmael F Santos

Anil Nanduri

Sitaram Yadavalli

Debra T Cohen

Satchit Jain

Jim Hermerding

David S Bormann

Paul S Diefenbaugh

Alon Naveh

James P Kardach

John S Howard

William A Stevens, Jr

Darren L Abramson

Robert L Farrell

Jorge Pedro Rodriguez

Shai Rotem

Ariel Berkovits

Siripong Sritanyaratana

Ying Cui

Joseph W Tsang

Mark A Blake

Siripong Sritanyarantana

Anh L Pham

Rob Strong

Vijay R Sar-Dessai

Rudi Rughoonundon

For one disclosed embodiment, a lower limit for a power consumption device may be identified. Performance of the power consumption device may be reduced in response to a determination that a temperature corresponding to the power consumption device exceeds a threshold. Performance reduction may be limited based on the lower limit. Other embodiments are also disclosed.

Performance reduction limit for power consumption device

Methods and apparatuses for intervening in the self power or thermal regulations of a plurality of independent power consumption devices are described herein. The novel methods may include monitoring power consumption and thermal conditions of the plurality of power consumption (i.e., power/heat dissipation) devices that are configured to independently self-regulate their power/thermal production. A determination may then be made as to whether an aggregate of the power and/or thermal production of the plurality of power consumption devices exceed a threshold. And if the aggregate of the power or thermal production of the power consumption devices was determined to exceed the threshold, terminating, at least partially, the independent self-regulating of the thermal production and intervening in the thermal regulation of one or more of the power consumption devices. In contrast, if the aggregate of the power and/or thermal production of the plurality of power consumption devices is determined to be below the threshold then the power consumption devices may be allowed to self-regulate their power consumptions, and in some instances, one or more of the individual power clamps for the one or more of the power consumption devices may be relaxed or raised.

Intervention of independent self-regulation of power consumption devices

Systems and methods of managing power provide for placing a processor in a non-snoopable state, where the processor is associated with a system memory. One or more data transfers between a controller and the system memory can be serviced while the processor is in the non-snoopable state. In one embodiment, it is determined that the processor has flushed an internal cache of the processor to the system memory before placing the processor in the non-snoopable state.

System and method of coherent data transfer during processor idle states

An audio noise mitigation approach. For one aspect, a first voltage associated with a first power management state is provided. A signal responsive to an indication associated with at least a first type of periodic exit event is received and responsive to the signal, a transition to a second voltage associated with a second state is initiated, a rate of the transition to the second voltage being slower than a similar voltage transition initiated in response to a non-periodic exit event.

Audio noise mitigation for power state transitions

Systems and methods of managing power consumption provide for placing a processor in a non-snoopable state while a storage interface associated with the processor is enabled for bus mastering. In one embodiment, the bus mastering results in traffic between the storage interface and a storage device, where the traffic is monitored and the processor is placed a snoopable state when traffic is moving, and in the non-snoopable idle state if the traffic ceases for a period of time.

Reducing storage data transfer interference with processor power management

Embodiments of the present invention provide a method and apparatus for conserving power in an electronic device. In particular, embodiments of the present invention dynamically place the memory in self-refresh and chipset clock circuits in power down mode while keeping the isochronous streams (such as display) updated and servicing bus master cycles in a power savings mode.

Method and apparatus for dynamic DLL powerdown and memory self-refresh

A circuit for monitoring future Universal Serial Bus (USB) activities is described. Specifically, the circuit may comprise a Direct Memory Access (DMA) engine schedule prefetcher. The DMA engine schedule prefetcher accesses linked list schedule structures in main memory. The structures are checked for future frames where the linked list has USB activity scheduled. A periodic DMA engine subsequently accesses main memory only during frames where USB traffic is scheduled.

USB schedule prefetcher for low power

In one embodiment, a data processing system includes, but is not limited to, a processor, a memory coupled to the processor, and a universal serial bus (USB) controller coupled to the processor and the memory. The USB controller includes a local memory to cache at least one activity descriptor of at least a portion of a periodic schedule having multiple frames stored in the main memory. The USB controller defers to service an active USB device described by one of the activity descriptors until a corresponding frame is scheduled to be serviced subsequently. Other methods and apparatuses are also described.

Method and apparatus to quiesce USB activities using interrupt descriptor caching and asynchronous notifications

One embodiment includes a future activity list (FAL) maintained within a peripheral bus host controller. The FAL includes information indicating for a number of peripheral bus frames whether those frames will have activity or are null. For frames that will have activity, the host controller performs a system memory read to gather information required to process the active frame. For frames that are null, the host controller does not perform the system memory read. A bus master status bit is pegged (continually set to 'true') by the host controller only when the host controller is processing an active frame. Because the bus master status bit is not pegged by the host controller during null frames, there is greater opportunity for an operating system to enter lower power states.

Future activity list for peripheral bus host controller

In accordance with an embodiment of the present invention, a triggering event is initiated to place a processor in a low power state. The processor may or may not flush a cache upon entering the low power state depending on a power status signal. The power status signal may indicated the relative priority of power reduction associated with placing the processor in the low power state without first flushing the cache versus an increase in soft error rate in the cache associated with reducing the voltage in the low power state.

Method and apparatus for enabling a low power mode for a processor

In one embodiment of the invention, an integrated device is described that employs a mechanism to control power consumption of a graphics memory controller hub (GMCH) through both voltage and frequency adjustment of clock signal received from a clock generator. The GMCH comprises a graphics core and a circuit to alter operational behavior, such as the frequency of a render clock signal supplied to the graphics core. The circuit is adapted to monitor idleness of the graphics core and reduce a frequency level of the render clock signal if the idleness exceeds a determined percentage of time.

Power management for an integrated graphics device

An embodiment of a system for avoiding race conditions when using edge-triggered interrupts includes a processor that asserts an interrupt pending signal in response to the receipt of an edge-triggered interrupt. A power management device receives the interrupt pending signal. If the processor is in a low power state when it asserts the interrupt pending signal, then the power management device causes the processor to enter a high power state to allow the processor to service the pending interrupt.

Method and apparatus for avoiding race condition with edge-triggered interrupts

An interface between an accelerated graphics port graphics controller (AGP-GC) and a core controller to prevent entry into a low power state from interfering with transfers to or from the AGP-GC that have been requested but not completed. The core controller can communicate to the AGP-GC an intent to enter a low power state, while the AGP-GC can communicate to the core controller the busy status of the AGP-GC. When the AGP-GC receives notice of an intent to enter a low power state, it can stop issuing requests to the core controller. When the core controller detects that the AGP-GC is busy, the core controller can postpone entry into the low power state until the AGP-GC completes any requests that are in progress. In an alternate use of the interface, if the AGP-GC wishes to make a request during a low power state, it can signal the core controller of this need by indicating a busy status, which can trigger the core controller to initiate an exit from the low power state.

Entering and exiting power managed states without disrupting accelerated graphics port transactions

A selectable control over multiple clock frequency/voltage level combinations that can be activated in a processor. A table can be placed in hardware that defines multiple combinations of CPU clock frequency and CPU operating voltage. By placing the table in hardware, it can be assured that all the various combinations will work for the particular processor device. Software can then be used to select a combination from this table, to control the actual frequency/voltage combination that is being implemented at a given time. This allows dynamic control over the power/performance tradeoff, so that the system can see maximum power savings consistent with acceptable performance, as operating and environmental considerations continue to change the most desirable selections.

System and method for selecting a frequency and voltage combination from a table using a selection field and a read-only limit field

In accordance with an embodiment of the present invention, a triggering event is initiated to place a processor in a low power state. The processor may or may not flush a cache upon entering the low power state depending on a power status signal. The power status signal may indicate the relative priority of power reduction associated with placing the processor in the low power state without first flushing the cache versus an increase in soft error rate in the cache associated with reducing the voltage in the low power state.

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Sunnyvale, CA, United States of America

Leslie E Cline