Sun Microsystems, Inc.

Lsi Logic Corporation

C-cube Microsystems, Inc.

Leslie Dean Kohn

Kevin B Normoyle

Satyanarayana Nishtala

Zahir Ebrahim

Louis F Coffin, Iii

Robert Yung

Timothy J Van Hook

William C Van Loo

Dale Robert Greenley

Charles E Narad

William Van Loo

Greg Williams

Ming Yeh

William N Joy

David Barr

Didier LeGall

Sun-den Chen

Thomas L Lyon

Kamil Metin Uz

Didier Le Gall

Diego P De Garrido

Ken Okin

A system controls reproduction of a video transmission between a transmitter and a receiver. The system includes an encryptor with an offset generator adapted to receive the encrypted frame key and to generate a sequence, of pseudo-random values for the color component; and an adder coupled to the offset generator and to the color component signal for providing an encoded color component signal. The system also includes a decryptor with a decryptor offset generator adapted to receive the encrypted frame key and to generate a decryptor pseudo-random value for the color component; and a subtractor coupled to the offset generator and to the color component signal for subtracting the offset signal from the color component signal.

Method of protecting high definition video signal

A method of motion compensation using temporal support of multiple fields of video to produce a progressive frame. The moving average of the motion compensated field lines temporally adjacent to the field to be de-interlaced are used, after a non-linear filtering, as the missing lines to complete the progressive video frame.

Motion compensated de-interlacing

An apparatus performs motion estimation based on an average of previous field references in a flexible, yet high performance manner. The apparatus has a command memory for storing a motion estimation command list segment which in turn contains a search command for specifying a merged search operation over one or more search positions. The apparatus also has a score memory for storing the result of each merged search operation. The score memory is initialized when the merged search operation is initiated. During the search operation, the score memory accumulates the result of each search position. The apparatus also has a search engine connected to the command memory and to the score memory for determining from the score memory a search position with the lowest score. The search engine then generates dual prime motion estimation outputs in the form of motion estimation result list segments.

Dual-prime motion estimation engine

An apparatus performs motion estimation based on a reference image and a target image. The apparatus has a command memory for storing a motion estimation command list segment and a search engine connected to the command memory. The search engine retrieves and processes the command list segment stored in the memory. The search engine in turn has a reference window memory containing one or more reference data segments, a target memory containing one or more target data segments, and a data path engine for generating a score for each offset between data in the reference window memory and data stored in the target memory. A result memory receives outputs from the motion estimation search engine in the form of motion estimation result list segments. The reference window memory, target memory, and result memory may be double-buffered to minimize system memory latencies. Moreover, target and reference fetches may be shared by up to four search targets in a split search command. Additionally, the command list segment and the result list segment use an identical format. The size of each command in the command list and each result in the result list is also identical. The identical format and size characteristics allow results generated by a current search to be reused as a part of the command for the next search.

Motion estimation engine

A process of synchronizing two execution units sharing a common memory with a plurality of memory banks starts by assigning a first memory bank to a one of two execution units. The other memory bank is assigned to the other execution unit. Then a sequence of operations is processed within one of the execution units while another sequence of operations is processed within the other execution unit. When the first execution unit completes a sequence of operations, a synchronizing operation is performed which causes that first execution unit to suspend processing if a corresponding sequence of operations in the other execution unit has not been completed. When both execution units have completed their respective sequences of operations, the assignment of memory banks is swapped between the two execution units, thereby preventing erroneous reads and writes.

Out of order instruction processing using dual memory banks

A separate cacheable-in-virtual-cache attribute bit (CV) is maintained for each page of memory in the translation table maintained by the operating system. The CV bit indicates whether the memory addresses on the page to which the translation table entry refers are cacheable in virtually indexed caches. According to a first embodiment, when there are two or more aliases which are not offset by multiples of the virtual cache size, all of the aliases are made non-cacheable in virtually indexed caches by deasserting the CV bits for all aliases. With regards to the contents of the translation lookaside buffer (TLB), the translations for all aliases may simultaneously coexist in the TLB because no software intervention is required to insure data coherency between the aliases. According to second and third embodiments of the present invention, when there are two or more aliases which are not offset by multiples of the virtual cache size, only one of those aliases may remain cacheable in virtual caches. For the other aliases, the CV bits for the translation pages containing those aliases are deasserted. The operating system has the responsibility of flushing data from the virtually indexed internal cache before deasserting the CV attribute for a page. The second embodiment allows the newer mapping to a physical address to remain in the first-level cache, while the third embodiment allows the older alias to remain in the first-level cache when a newer alias is mapped.

Cachability attributes of virtual addresses for optimizing performance

The integer execution unit (IEU) of a central processing unit (CPU) is provided with a graphics status register (GSR) for storing a graphics data scaling factor and a graphics data alignment address offset. Additionally, the CPU is provided with a graphics execution unit (GRU) for executing a number of graphics operations in accordance to the graphics data scaling factor and alignment address offset, the graphics data having a number of graphics data formats. In one embodiment, the GRU is also used to execute a number of graphics data addition, subtraction, rounding, expansion, merge, alignment, multiplication, logical, compare, and pixel distance operations. The graphics data operations are categorized into a first and a second category, and the GRU concurrently executes one graphics operations from each category. Furthermore, under this embodiment, the IEU is also used to execute a number of graphics data edge handling and 3-D array addressing operations, while the load and store unit (LSU) of the CPU is also used to execute a number of graphics data load and store operations, including conditional store operations.

Central processing unit with integrated graphics functions

A partial store instruction and associated logic for storing selected bytes of a group of bytes in a register to a designated memory location. A mask in a separate register is used to enable particular bytes to be written, with only enabled bytes being written to the final location. The mask can be previously generated as a result of a comparison or other operation. The creation of the mask and the execution of a partial store instruction can also be used as a prefetch instruction, eliminating the need for a separate opcode for a prefetch.

Graphic system for masking multiple non-contiguous bytes having decode

This invention describes a link-by-link flow control method for packet-switched uniprocessor and multiprocessor computer systems that maximizes system resource utilization and throughput, and minimizes system latency. The computer system comprises one or more master interfaces, one or more slave interfaces, and an interconnect system controller which provides dedicated transaction request queues for each master interface and controls the forwarding of transactions to each slave interface. The master interface keeps track of the number of requests in the dedicated queue in the system controller, and the system controller keeps track of the number of requests in each slave interface queue. Both the master interface, and system controller know the maximum capacity of the queue immediately downstream from it, and does not issue more transaction requests than what the downstream queue can accommodate. An acknowledgment from the downstream queue indicates to the sender that there is space in it for another transaction. Thus no system resources are wasted trying to send a request to a queue that is already full.

Method and apparatus for flow control in packet-switched computer system

A method and apparatus for dynamically switching the relative priorities of the load buffer and store buffer with respect to external memory resources in a superscalar processor. According to a first embodiment, a protocol dictates that the load buffer always prevails until the store buffer reaches a certain 'high water mark,' (an upper threshold) at which time the store buffer gains priority. After the store buffer has gained priority, it continues to access the memory until it is depleted to a 'low water mark,' (a lower threshold) at which time the load buffer regains priority. Whenever the store buffer reaches the high water mark, it gains priority until it drains down to the low water mark. This reduces the tendency for the store buffer to become full and block the processor. According to a second embodiment, the load buffer prevails if it is above its high water mark. If the load buffer is below its high water mark, the load buffer prevails until the store buffer reaches its high water mark, at which time the store buffer gains priority. After the store buffer has gained priority, it maintains priority until the load buffer reaches its high water mark. This reduces the tendency for either buffer to become full and block the processor.

Dynamic priority switching of load and store buffers in superscalar

A non-fault-only (NFO) bit is included in the translation table entry for each page. If the NFO bit is set, non-faulting loads accessing the page will cause translations to occur. Any other access to the non-fault-only page is an error, and will cause the processor to fault. A non-faulting load behaves like a normal load except that it never produces a fault even when applied to a page with the NFO bit set. The NFO bit in a translation table entry marks a page that is mapped for safe access by non-faulting loads, but can still cause a fault by other, normal accesses. The NFO bit indicates which pages are illegal. Selected pages, such as the virtual page 0x0, can be mapped in the translation table. Whenever a null-pointer is dereferenced by a non-faulting load, a translation lookaside buffer (TLB) hit will occur, and zero will be returned immediately without trapping to software to find the requested page. A second embodiment provides that when the operating system software routine invoked by a TLB miss discovers that a non-faulting load has attempted to access an illegal virtual page that was not previously translated in the translation table, the operating system creates a translation table entry for that virtual page mapping it to a physical page of all zeros and asserting the NFO bit for that virtual page.

Method and apparatus for implementing non-faulting load instruction

A dual-ported tag array of a cache allows simultaneous access of the tag array by miss data of older LOAD instructions being returned during the same cycle that a new LOAD instruction is accessing the tag array to check for a cache hit. Because a load buffer queues LOAD instructions, the cache tags for older LOAD instructions which missed the cache return later when new LOAD instructions are accessing a tag array to check for cache hits. A method and apparatus for calculating and maintaining a hit bit in a load buffer perform the determination of whether or not a newly dispatched LOAD will hit the cache after it has been queued into the load buffer and waited for all older LOADs to be processed. A load buffer data entry includes the hit bit and all information necessary to process the LOAD instruction and calculate the hit bits for future LOAD instructions which must be buffered. A method and apparatus for servicing LOAD instructions, in which the access of the data array portion of a cache and the tag array portion are decoupled, allows the delayed access of the data array after a LOAD has been delayed in the load buffer without reaccessing the tag array.

Hit bit for indicating whether load buffer entries will hit a cache when

A dual-ported tag array of a cache allows simultaneous access of the tag array by miss data of older LOAD instructions being returned during the same cycle that a new LOAD instruction is accessing the tag array to check for a cache hit. Because a load buffer queues LOAD instructions, the cache tags for older LOAD instructions which missed the cache return later when new LOAD instructions are accessing a tag array to check for cache hits. A method and apparatus for calculating and maintaining a hit bit in a load buffer perform the determination of whether or not a newly dispatched LOAD will hit the cache after it has been queued into the load buffer and waited for all older LOADs to be processed. A load buffer data entry includes the hit bit and all information necessary to process the LOAD instruction and calculate the hit bits for future LOAD instructions which must be buffered. A method and apparatus for servicing LOAD instructions, in which the access of the data array portion of a cache and the tag array portion are decoupled, allows the delayed access of the data array after a LOAD has been delayed in the load buffer without reaccessing the tag array. A method and apparatus allow access to the first level cache and second level cache to occur simultaneously for two separate LOADs in the load buffer.

Methods and apparatuses for servicing load instructions

A computer system is disclosed including a memory subsystem and a processor subsystem having an external cache and an external mechanism for invalidating cached datablocks in the processor subsystem and for reducing false invalidation operations. The processor subsystem issues a write invalidate message to the memory subsystem that specifies a datablock and that includes an invalidate advisory indication that indicates whether the datablock is present in the external cache. The invalidate advisory indication determines whether the memory subsystem returns an invalidate message to the processor subsystem for the write invalidate operation.

Growing community of inventors

Fremont, CA, United States of America

Leslie Dean Kohn