International Business Machines Corporation

Leslie C Jenkins

Robert L Wisnieff

Robert J Polastre

Frank Robert Libsch

Michael Patrick Mastro

Robert Wayne Nywening

Shinichi Kimura

Ronald R Troutman

Yoshikazu Ichioka

A device for use in a display system including an array of pixel cells formed on a substrate. Each pixel cell being coupled to at least one gate line of a plurality of gate lines formed on the substrate and at least one data line of a plurality of data lines being formed on the substrate. The device includes first and second transistors formed on the substrate. Each transistor has a gate electrode and first and second electrodes defining a serpentine channel region there between voltage applied to the gate electrode controls conductivity of the channel region. Preferably, a common electrode includes one of the first and second electrodes of the first transistor and one of the first and second electrodes of the second transistor. The first and second transistors are preferably coupled between a gate line (or data line) and respective probe pads formed on the substrate and selectively couple the respective probe pad to the gate line (or data line) during a test routine whereby charge is written to, stored, and read from the array of pixel cells.

Integrated circuits for testing an active matrix display array

An improved apparatus for testing an array of pixel cells formed on a substrate is provided. Each pixel cell is coupled to at least one gate line of a plurality of gate lines formed on the substrate and at least one data line of a plurality of data lines formed on the substrate. The gate lines and/or data lines are partitioned into a plurality of groups. For each particular group, a first probe pad and select logic is formed on said substrate. The select logic, which is coupled between the first probe pad and the lines of the particular group, selectively couples the first probe pad to the lines of said particular group based upon first control signals supplied to the select logic during a test routine whereby charge is written to, stored, and read from the array of pixel cells. In addition, a second probe pad and hold logic for each particular group may be formed on the substrate. The hold logic, which is coupled between the second probe pad and the lines of the particular group, selectively couples the second probe pad to the lines of the particular group based upon second control signals supplied to the hold logic during the test routine. The apparatus provides a flexible interface between the array under test and the test system, which minimizes the redesign costs when the size and/or resolution of the array under test is varied.

Integrated circuits for testing a display array

A sense circuit for detecting charge on a TFT/LCD cell capacitor, which comprises a first, integrating circuit attached to the TFT/LCD cell capacitor through a data line, wherein the data line is connected to the cell capacitance through a thin film transistor is disclosed. The thin film transistor including a gate, a drain and a source, wherein the source is connected to the cell capacitor and the drain is connected to the data line. A first, gate supply voltage adapted to drive the gate of the thin film transistor. And a reset circuit adapted to reset the integrating circuit. This embodiment may further include a source for charging said cell capacitor prior to measuring the charge. Further, a method of testing a partially constructed electronic circuit, for example the cell of an LCD, prior to installation of the backplate is also disclosed. The partial circuit comprising an array of contact electrodes, for example cell pad electrodes and an array of address electrodes, for example gate electrodes. The address electrodes being electrically connected to the contact electrodes. The method comprising the steps of providing the partial circuit with a test electrode, for example an adjacent data electrode extending alongside but spaced from at least a first contact electrode; and measuring the capacitance between the first contact electrode and the test electrode.

Method for testing a partially constructed electronic circuit

An apparatus for testing for and classifying defects in a TFT/LCD array having gate lines and data lines. Devices are provided for activating cells of the array by applying gate pulses to the gate lines and pulses to the data lines. Devices are also provided for acquiring waveforms from data lines of the array. Additional devices sample the waveforms at selected points in time. A computer may be used to classify the waveforms to indicate whether defects are present and if present, the nature of the defects by comparing voltages of the waveform at the selected points in time.

Array tester for determining contact quality and line integrity in a

A sense circuit for detecting charge on a TFT/LCD cell capacitor, which comprises a first, integrating circuit attached to the TFT/LCD cell capacitor through a data line, wherein the data line is connected to the cell capacitance through a thin film transistor. The thin film transistor including a gate, a drain and a source, wherein the source is connected to the cell capacitor and the drain is connected to the data line. A first, gate supply voltage adapted to drive the gate of the thin film transistor. And a reset circuit adapted to reset the integrating circuit. This embodiment may further include a source for charging said cell capacitor prior to measuring the charge. Further, a method of testing a partially constructed electronic circuit, for example the cell of an LCD, prior to installation of the backplate. The partial circuit comprising an array of contact electrodes, for example cell pad electrodes and an array of address electrodes, for example gate electrodes. The address electrodes being electrically connected to the contact electrodes. The method comprising the steps of providing the partial circuit with a test electrode, for example an adjacent data electrode extending alongside but spaced from at least a first contact electrode; and measuring the capacitance between the first contact electrode and the test electrode.

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Holmes, NY, United States of America

Leslie C Jenkins