Intel Corporation

Leopoldo D Yau

Robert S Chau

Chan-Hong Chern

Chia-Hong Jan

Kenneth C Cadien

Galen H Kawamoto

David B Fraser

Paul A Packan

Michael R Oliver

Stephen T Chambers

Joseph R Breivogel

Shih-Ou Chen

Christopher E Barns

Jick M Yu

Kevin R Weldon

William L Hargrove

Robert A Gasser, Jr

Yih S Lin

Samuel F Louke

Brian J Brown

Gopal Raghavan

David D Chin

Kenneth R Week, Jr

Brian S Doyle

Paul B Fischer

Shahriar S Ahmed

Chi-Hwa Tsang

George E Sery

Philip E Freiberger

Robert F Hainsey

Robert S K Chau

Cheng-Sheng Pan

Robert J Stoner

Todd E Wilke

Quat T Yu

A novel process for forming a robust, sub-100 &angst; oxide is disclosed. Native oxide growth is tightly controlled by flowing pure nitrogen during wafer push and nitrogen with a small amount of oxygen during temperature ramp and stabilization. First, a dry oxidation is performed in oxygen and 13% trichloroethane. Next, a wet oxidation in pyrogenic steam is performed to produce a total oxide thickness of approximately 80 &angst;. The oxide layer formed is ideally suited for use as a high integrity gate oxide below 100 &angst;. The invention is particularly useful in devices with advanced, recessed field isolation where sharp silicon edges are difficult to oxidize. For an oxide layer of more than 100 &angst;, a composite oxide stack is used which comprises 40-90 &angst; of pad oxide formed using the above novel process, and 60-200 &angst; of deposited oxide.

Process for forming a thin oxide layer

A novel transistor with a low resistance ultra shallow tip region and its method of fabrication. The novel transistor of the present invention has a source/drain extension or tip comprising an ultra shallow region which extends beneath the gate electrode and a raised region.

Transistor with ultra shallow tip and method of fabrication

A novel transistor with a low resistance ultra shallow tip region and its method of fabrication in a complementary metal oxide semiconductor (CMOS) process. According to the preferred method of the present invention, a first gate dielectric and a first gate electrode are formed on a first portion of a semiconductor substrate having a first conductivity type, and a second gate dielectric and a said gate electrode are formed on a second portion of semiconductor substrate having a second conductivity type. A silicon nitride layer is formed over the first portion of the semiconductor substrate including the first gate electrode and over the second portion of the semiconductor substrate including the second gate electrode. The silicon nitride layer is removed from the second portion of the silicon substrate and from the top of the second gate electrode to thereby form a first pair of silicon nitride spacers adjacent to opposite sides of the second gate electrode. A pair of recesses are then formed in the second portion of the semiconductor substrate in alignment with the first pair of sidewall spacers. A selectively deposited semiconductor material is then formed in the recesses.

Transistor with low resistance tip and method of fabrication in a CMOS

A semiconductor wafer polishing pad conditioner which includes a support structure and a roller which is rotatably mounted to the support structure. The roller has a working surface which is formed with a plurality of blades.

Apparatus and a method for conditioning a semiconductor wafer polishing

A method and apparatus for polishing a thin film formed on a semiconductor substrate. A table covered with a polishing pad is orbited about an axis. Slurry is fed through a plurality of spaced-apart holes formed through the polishing pad to uniformly distribute slurry across the pad surface during polishing. A substrate is pressed face down against the orbiting pad's surface and rotated to facilitate, along with the slurry, the polishing of the thin film formed on the substrate.

Orbital motion chemical-mechanical polishing method and apparatus

The present invention provides an interconnect system. The interconnect system includes a substrate, a first dielectric layer deposited upon the substrate. The interconnect system further includes at least two electrically conductive interconnect lines formed upon the first dielectric layer. Each of the at least two interconnect lines have a top surface and side surfaces. Adjacent side surfaces of two adjacent interconnect lines define therebetween a space that has a dielectric constant substantially equal to 1. A dielectric film is bonded upon the top surface of the at least two interconnect lines. The dielectric film substantially prevents obstruction of the space by further process.

Capping layer in interconnect system and method for bonding the capping

A new method of isolating a polysilicon emitter from the base region of a bipolar transistor, trenching the polysilicon emitter into the semiconductor substrate, and maintaining a consistent base width of a bipolar transistor independent of variations in emitter mask thicknesses is disclosed. The polysilicon emitter isolation provides for better electrical breakdown characteristics between the emitter and the base by protecting the dielectric layer between the polysilicon emitter and base regions from defects and contamination associated with the BiCMOS manufacturing environment. The polysilicon emitter is trenched into the semiconductor substrate in order to reduce transistor operation problems associated with hot electron injection. Consistent base widths improve transistor performance uniformity thereby improving manufacturability and reliability.

Integrated dual layer emitter mask and emitter trench for BiCMOS

A novel, reliable, high performance MOS transistor with a composite gate electrode which is compatible with standard CMOS fabrication processes. The composite gate electrode comprises a polysilicon layer formed on a highly conductive layer. The composite gate electrode is formed on a gate insulating layer which is formed on a silicon substrate. A pair of source/drain regions are formed in the substrate and are self-aligned to the outside edges of the composite gate electrode.

Method of frabricating a MOS transistor having a composite gate electrode

A novel transistor with a low resistance ultra shallow tip region and its method of fabrication. The novel transistor of the present invention has a source/drain extension or tip region comprising an ultra shallow region which extends beneath the gate electrode and a raised region.

MOS transistor having a composite gate electrode and method of

A method and apparatus for conditioning and/or rinsing a pad in a chemical-mechanical polisher. A scoring apparatus is rotated about its center directly over the polishing pad of the chemical-mechanical polisher. The scoring apparatus scores the pad surface while rotating above the pad. Consequently the pad is conditioned in a uniform and concentric fashion.

Method and apparatus for conditioning of chemical-mechanical polishing

A method for polishing the surface of a substrate that overcomes the problems inherent in the prior art. During the polishing of a substrate, a quantity is calculated which is approximately proportional to a share of the total energy the polisher is consuming. Once this calculated quantity reaches a predetermined amount, it is detected.

Method and apparatus for endpoint detection in a chemical/mechanical

Orbital motion chemical-mechanical polishing apparatus and method of

Method of making emitter trench BiCMOS using integrated dual layer

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Portland, OR, United States of America

Leopoldo D Yau