Micron Technology Incorporated

Western Digital Technologies, Inc.

Sandisk Il Ltd.

Sandisk Technologies Inc.

Leonid Minz

Leon Zlotnik

Shay Benisty

Yoav Weinberg

Ekram H Bhuiyan

Boris Dolgunov

Roy Krotman

Eric N Lee

Luigi Pilolli

Ali Feiz Zarrin Ghalam

Tal Sharifie

Itai Dror

Yair Baram

Michael Tomashev

Avraham Poza Meir

Dmitry Vaysman

Yan Dumchin

Hanan Borukhov

Vitali Linkovsky

Pranjal Chauhan

Simon Bass

Suzanna Zilberman

Michael Koun

Michael Kun

Ron Tsechanski

Yevgeny Kaplan

Clock enable signals are collected and summed. The number of simultaneously enabled clock enable signals can represent switching activity within a system and can be used as an indicator for power management, noise management, etc. of such a system. Digital switching activity sensing include performance of an operation to sum a quantity of open clock gates associated with a plurality of latches that are grouped into multiple subsets of latches. An activity indication is generated based, at least in part, on a result of the operation to sum the quantity of open clock gates associated with the plurality of latches.

Digital switching activity sensing

Operations include monitoring a logical level of a first pin of the plurality of pins while a data burst is active, wherein the first pin is associated with at least one of a read enable signal or a data strobe signal, determining whether a period of time during which the logical level of the first pin is held at a first logical level satisfies a threshold condition, in response to determining that the period of time satisfies the threshold condition, continuing to monitor the logical level of the first pin, determining whether the logical level of the first pin changed from the first logical level to a second logical level, and in response to determining that the logical level of the first pin changed from the first logical to the second logical level, causing warmup cycles to be performed.

Data burst suspend mode using pause detection

An example method for scan-based voltage frequency scaling can include performing a plurality of at-speed scan operation on a system on chip (SoC) at a plurality of respective voltage values. The example method can include entering data gathered from at least one of the plurality of at-speed scan operations into a database. The entered data is associated with the respective plurality of voltage value. The example method can include determining a particular voltage value of the respective plurality of voltage values at which a parameter of the SoC reaches a threshold. The example method can include indicating the determined particular voltage in the database. The indicated determined particular voltage in the database can be used for performing one or more operations using the SoC.

Scan-based voltage frequency scaling

A memory device includes a memory array and processing logic, operatively coupled with the memory array, to perform operations including causing a data burst to be initiated by toggling a logical level of a control pin from a first level corresponding to a data burst inactive mode to a second level corresponding to a data burst active mode, wherein the data burst corresponds to a data transfer across an interface bus, causing the data burst to be suspended by toggling the logical level of the control pin from the second level to a third level corresponding to a data burst suspend mode, and causing the data burst to be resumed by toggling the logical level of the control pin from the third level to the second level.

Data burst suspend mode using multi-level signaling

A plurality of flip-flops of an integrated circuit (IC) (e.g., an ASIC) are electrically connected in a predefined series. The scan input gate of any give flip-flop in the predefined series is electrically connected to one of a Q output gate or a Q-bar output gate of an adjacent flip-flop in the predefined series. A reset operation for the IC occurs by feeding a bit string of identical bits (e.g., all zeros) through the scan input gate of a first flip-flop of the plurality of flip-flops to reset the plurality of flip-flops without the need for resetting circuitry and accompanying power savings for the IC.

Resetting integrated circuits

A voltage tracking circuit includes delay line blocks, a phase detector delay line block, phase detection circuitry, and a controller. The controller determines a first voltage based on a quantity of active delay line blocks among the plurality of delay line blocks and determines a second voltage based on information received from the phase detection circuitry. The controller determines a measured value of a voltage provided by the voltage regulator voltage based on the first voltage and the second voltage.

Voltage tracking circuit

Sensing circuitry and clock management circuitry provide transient load management. The sensing circuitry detects a voltage, current, and/or activity associated with a system-on-chip (SoC) and determines whether the detected voltage, current, and/or activity meets a threshold. The clock management circuitry generates clocking signals for the SoC and alters a frequency of the generated clocking signals in response to the detected voltage, current, and/or activity meeting the threshold to alter an amount of power consumed by the SoC.

Transient load management for a system-on-chip meeting an activity threshold

A method includes receiving a respective signal from each of a plurality of respective sensor circuits, wherein each respective signal is indicative of a voltage or a current detected by each of the plurality of respective sensor circuits and performing an operation to determine whether one or more of the received signals meets a criterion. The method further includes generating a voltage management control signal in response to a determination that the one or more of the received signals meets the criterion, transferring the voltage management control signal to a voltage regulator, and generating, by the voltage regulator, a voltage signal in response to receipt of the voltage management control signal.

Voltage management system

Aspects of the present disclosure are directed to multi-referenced power supplies. One method includes sensing each voltage, via a voltage sensor, of plurality of voltages from different areas of circuit components prior to the voltage reaching a voltage regulator, receiving, at a voltage manager, a sensed voltage magnitude from the voltage sensor, and selecting a feedback voltage to be provided to the voltage regulator based on the sensed voltage magnitude from the voltage sensor for the at least one of the plurality of voltages.

Multi-referenced power supply

Aspects of the present disclosure are directed to voltage drop compensation for power supplies. One method includes sensing each voltage, via a voltage sensor, of a plurality of voltages from different areas of circuit components prior to the voltage reaching a voltage regulator, receiving, at a voltage manager, a sensed voltage magnitude from the voltage sensor for at least one of the plurality of voltages, receiving, at a voltage manager, data for a number of characteristics of the circuitry components, and selecting a correction voltage to be provided to the voltage regulator based on the sensed voltage magnitude from the voltage sensor for the at least one of the plurality of voltages and data for at least one of the characteristics of the circuitry components.

Power supply voltage drop compensation

A voltage sensing circuit includes voltage regulators, oscillator circuits, delay circuits, and a detector circuit. The detector circuit detects characteristics of signaling received from a first oscillator circuit and characteristics of signaling received from a second oscillator circuit. The detector circuit compares the detected characteristics of the signaling from the first oscillator circuit and the second oscillator circuit to determine whether the detected characteristics from the first oscillator circuit and the second oscillator circuit meet a particular criterion for providing voltage manipulation for the voltage sensing circuit.

Voltage sensing circuit

Memory units are accessed using address bits. The address bits used to access memory units can have various formats. The address bits to access successive locations that are to be sequentially accessed can have a reduced Hamming distance binary code format to reduce a quantity of toggling to switch from one set of address bits to another set of address bits.

Address bits with reduced hamming distance

The present disclosure generally relates to a method and device for accessing more dies per channel in a data storage device. Each flash interface module (FIM) can have any number of bus multiplexers coupled thereto, and each bus multiplexer can have any number of memory devices coupled thereto. The bus multiplexers can be connected in series or in parallel to the FIM. The individual bus multiplexers can be addressed by a chip enable (CE) command that identifies the specific bus multiplexer as well as the specific memory device of the specific bus multiplexer. The information in the CE command allows more dies per channel without creating signal interference (SI) or limiting transmission performance.

Advanced CE encoding for bus multiplexer grid for SSD

A method of accessing a storage device, including receiving, by a controller of the storage device, a host-write transaction directed to a memory space defined within the controller. The controller then classifies the host-write transaction based on a type of the host-write transaction to generate a classified transaction, and generates parity data based on the classified transaction. The controller stores data associated with the host-write transaction and the parity data in a memory of the controller. The method includes determining a destination address of the classified transaction and classifying, based on the destination address. Generating the parity data includes determining an allocated block size associated with the destination address and generating the parity data based on the allocated block size. The allocated block size varies based on the destination address. The method additionally includes translating the host-write transaction from a first protocol to a Non-Volatile Memory Express (NVMe) protocol.

Partitioned non-volatile memory express protocol for controller memory buffer

A controller includes one or more hardware components for performing operations, an interconnect, and a plurality of processors connected to the one or more hardware components through the interconnect. Each processor of the plurality of processors is configured to perform multithreading to concurrently handle multiple threads of execution, and assign a different thread identifier or master ID value to each concurrently handled thread of execution. An instruction is generated for a hardware component by executing a thread of the concurrently handled threads of execution. The instruction includes the thread identifier or indicates the master ID value assigned to the thread. The generated instruction is sent to the hardware component through the interconnect.

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Beer Sheva, Israel

Leonid Minz