National Semiconductor Corporation

Technion Research & Development Foundation Ltd

Winbond Electronics Corporation

Leonid Azriel

Ohad Falik

Nir Tasher

Ran Ginosar

Shahar Kvatinsky

Abraham Mendelson

Valery Teper

Ziv Hershman

Assaf Koren

Apparatus and method for hashing a message, comprises using an array of individually selectable memristor cells. The memristor cells are subject to write disturb that affects cells neighboring a selected cell so that a write operation into one cell has a knock-on effect on the neighbors. The array is initiated into a known stable state so that these changes to neighboring cells are predictable according to proximity to the currently selected cell. An inserter sequentially mixes bits with the hash so far to insert bits into successively selected cells of the memristor array and forms a succession of memristor array states including the knock on effects on the neighboring cells. A final resulting memristor array state following input of the bits forms the hash of the message.

Memresistive security hash function

A computerized method of creating a circuit logic model of a VLSI device, comprising mapping a plurality of logic function patterns of one or more circuits of a VLSI device through a plurality of probe iterations and generating a circuit logic model of the circuit(s) by reconstructing a logical function of a combinatorial logic of the circuit(s) based on analysis of the logic function patterns. Each of the probe iteration comprises switching between scan shift mode and functional mode of the VLSI device such that while the VLSI device operates in scan shift mode register(s) associated with the circuit(s) is accessed and while the VLSI device operates in functional mode external pin(s) of the VLSI device associated with the circuit(s) is probed and mapping a respective one of the logic function patterns according to a logic state of one or more bits in the register(s) and/or the external pin(s).

Exploiting the scan test interface for reverse engineering of a VLSI device

An Integrated Circuit (IC) includes signal distribution circuitry and protection circuitry. The signal distribution circuitry is configured to distribute a high-fanout signal across the IC. The protection circuitry includes a plurality of logic stages and detection circuitry. The logic stages are configured to receive multiple instances of the signal that are sampled at multiple sampling points in the signal distribution circuitry. The logic stages are interconnected to drive one another in accordance with a given topology so as to propagate abnormalities indicative of faults occurring in the signal distribution circuitry. The detection circuitry is configured to detect a fault in the signal distribution circuitry in response to an abnormality propagating in the plurality of logic stages.

Fault protection for high-fanout signal distribution circuitry

A semiconductor device includes an interface controller for communication with a memory device over a communication link. The link includes a plurality of data lines for transmitting data. A plurality of bus width values are defined, each being a selectable number of data lines over which data are to be transmitted. The number of data lines is in the range between one and the number of the plurality of data lines. The interface controller is dynamically configurable to any of the defined bus width values, which becomes the current bus width. The transmission over each data line may be selectably in either direction. The transmission over all data lines corresponding to the current bus width may collectively carry, in at least one direction, command codes, memory addresses, and data in an intermixed manner.

Memory interface including an efficient variable-width bus

Apparatus for limiting an output signal frequency of an on-chip clock generator is presented. Electronic circuitry compares the value of a ratio between the internal clock signal frequency and the reference clock input signal frequency with minimum and maximum calibration word signals, in order to determine if the reference clock input signal frequency is within a permitted range. If the reference clock input signal frequency is not within the permitted range, the apparatus sends a tamper alert to the chip or to a system, and the output clock signal frequency is not changed according to the reference clock input signal frequency, thereby protecting the chip from erroneous or tampered clock signal. The output clock signal is buffered from the reference clock input signal insuring that the output clock signal frequency is within the permitted range. The apparatus can operate without providing the reference input clock signal.

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Haifa, Israel

Leonid Azriel