Intel Corporation

Other

Leonel R Arana

Jeremy D Ecton

Changhua Liu

Robert Alan May

Brandon C Marin

Rajasekaran Swaminathan

Xiaoying Guo

Aleksandar Aleksov

Yoshihiro Tomita

Dingying David Xu

Steve S Cho

Oscar Ojeda

Rahul N Manepalli

Gang Duan

Suddhasattwa Nad

Yosuke Kanaoka

Srinivas V Pietambaram

Nachiket R Raravikar

Tarek A Ibrahim

Hiroki Tanaka

Edward Rudolph Prack

Jorge A Sanchez

Mohit Mamodia

Devendra Natekar

Hongxia Feng

Shankar Ganapathysubramanian

Arnab Roy

Haobo Chen

Vahidreza Parichehreh

Michael W Newman

Nitin A Deshpande

Zhiguo Qian

John Heck

Eric Jin Li

James Chris Matayabas, Jr

Yonggang Li

Robert M Nickerson

Carl L Deppisch

Sandeep B Sane

Stephen Edward Lehman, Jr

Sriram Srinivasan

Deepak Kulkarni

Lakshmi Supriya

Jung Kyu Han

Matthew L Tingey

Benjamin Duong

James P Mellody

George Vakanas

George S Kostiew

Gregory S Constable

Hsin-Wei Wang

Chung Kwang Tan

Raj Bahadur

Kyle Mcelhinny

Jiraporn Seangatith

Poh Chieh Benny Poon

Jessica A Weninger

Lateef Mustapha

Kristof Darmawikarta

John Stephen Guzek

Sanka Ganesan

Pooya Tadayon

Ram S Viswanath

Je-Young Chang

Daewoong Suh

Charan K Gurumurthy

Sri Chaitra Jyotsna Chavali

Nicholas S Haehn

Deepak Goyal

Amram Eitan

Terry Lee Sterrett

Bai Nie

Vijay Wakharkar

Zhiyong Wang

Marcel Arlan Wall

Sashi S Kandanur

Nirupama Chakrapani

Srinivas Venkata Ramanuja Pietambaram

Hari Mahalingam

Ali Lehaf

Jieying Kong

Kevin T McCarthy

Nilanjan Z Ghosh

Bohan Shan

Sarah Blythe

Keith J Martin

Wen Feng

Wendy Chan

Rob Nickerson

Lim Chong Sim

Sudhakar N Kulkarni

Yuelin Lee Zou

Onur Ozkan

Alexander Aguinaga

Yiyang Zhou

Daryl Purcell

Jason Steill

Whitney Bryks

A patch structure of an integrated circuit package comprises a core having a first side facing downwards and a second side facing upwards. A first solder resist (SR) layer is formed on the first side of the core, wherein the first SR layer comprises a first layer interconnect (FLI) and has a first set of one or more microbumps thereon to bond to one or more logic die. A second solder resist (SR) layer is formed on the second side of the core, wherein the second SR layer has a second set of one or more microbumps thereon to bond with a substrate. One or more bridge dies includes a respective sets of bumps, wherein the one or more bridge dies is disposed flipped over within the core such that the respective sets of bumps face downward and connect to the first set of one or more microbumps in the FLI.

First layer interconnect first on carrier approach for EMIB patch

Position controlled waveguides and methods of manufacturing the same are disclosed. An example apparatus includes a substrate with a channel that extends into a first surface of the substrate to a second surface of the substrate, wherein the second surface is recessed relative to the first surface; buffer material having a first index of refraction on the second surface of the substrate; and a waveguide on the buffer material, the waveguide having a second index of refraction that is higher than the first index of refraction.

Position controlled waveguides and methods of manufacturing the same

Various embodiments disclosed relate to photonic assemblies. The present disclosure includes methods for packaging a photonic assembly, including attaching a bridge die to a glass substrate, attaching an electronic integrated circuit die to the glass substrate and the bridge die, attaching a photonic integrated circuit die to the glass substrate and the bridge die, bonding a coupling adapter to the glass substrate and in situ forming a waveguide in the coupling adapted, the waveguide aligning with the photonic integrated circuit die.

Die last and waveguide last architecture for silicon photonic packaging

Methods and apparatus to reduce defects in interconnects between semiconductor dies and package substrates are disclosed. An apparatus includes a substrate and a semiconductor die mounted to the substrate. The apparatus further includes bumps to electrically couple the die to the substrate. Ones of the bumps have corresponding bases. The bases have a shape that is non-circular.

Methods and apparatus to reduce defects in interconnects between semiconductor dies and package substrates

Methods and apparatus to reduce defects in interconnects between semiconductor dies and package substrates are disclosed. An apparatus includes a substrate and a semiconductor die mounted to the substrate. The apparatus further includes an array of bumps to electrically couple the die to the substrate. Each of the bumps have a corresponding base. Different ones of the bases have different widths that vary spatially across the array of bumps.

Methods and apparatus to reduce defects in interconnects between semicondcutor dies and package substrates

Processes and structures resulting therefrom for the improvement of high speed signaling integrity in electronic substrates of integrated circuit packages, which is achieved with the formation of airgap structures within dielectric material(s) between adjacent conductive routes that transmit/receive electrical signals, wherein the airgap structures decrease the capacitance and/or decrease the insertion losses in the dielectric material used to form the electronic substrates.

Airgap structures for high speed signal integrity

An integrated circuit (IC) package substrate, comprising a metallization level within a dielectric material. The metallization level comprises a plurality of conductive features, each having a top surface and a sidewall surface. The top surface of a first conductive feature of the plurality of conductive features has a first average surface roughness, and the sidewall surface of a second conductive feature of the plurality of conductive features has a second average surface roughness that is less than the first average surface roughness.

Selectively roughened copper architectures for low insertion loss conductive features

Conductive routes for an electronic substrate may be fabricated by forming an opening in a material, using existing laser drilling or lithography tools and materials, followed by selectively plating a metal on the sidewalls of the opening. The processes of the present description may result in significantly higher patterning resolution or feature scaling (up to 2× improvement in patterning density/resolution). In addition to improved patterning resolution, the embodiments of the present description may also result in higher aspect ratios of the conductive routes, which can result in improved signaling, reduced latency, and improved yield.

Conductive route patterning for electronic substrates

Embodiments disclosed herein include electronic packages and methods of forming such packages. In an embodiment, the electronic package comprises a substrate and a conductive feature over the substrate. In an embodiment, a metallic mask is positioned over the conductive feature. In an embodiment, the metallic mask extends beyond a first edge of the conductive feature and a second edge of the conductive feature.

Subtractive etch resolution implementing a functional thin metal resist

A conductive route for an integrated circuit assembly may be formed using a sequence of etching and passivation steps through layers of conductive material, wherein the resulting structure may include a first route portion having a first surface, a second surface, and at least one side surface extending between the first surface and the second surface, an etch stop structure on the first route portion, a second route portion on the etch stop layer, wherein the second route portion has a first surface, a second surface, and at least one side surface extending between the first surface and the second surface, and a passivating layer abutting the at least one side surface of the second route portion.

Embodiments include a package structure with one or more layers of dielectric material, where an interconnect bridge substrate is embedded within the dielectric material. One or more via structures are on a first surface of the embedded substrate, where individual ones of the via structures comprise a conductive material and have a tapered profile. The conductive material is also on a sidewall of the embedded substrate.

Via structures having tapered profiles for embedded interconnect bridge substrates

Embodiments disclosed herein include a lithographic patterning system and methods of using such a system to form a microelectronic device. The lithographic patterning system includes an actinic radiation source, a stage having a surface for supporting a substrate with a resist layer, and a prism with a first surface over the stage, where the first surface has a masked layer and is substantially parallel to the surface of the stage. The prism may have a second surface that is substantially parallel to the first surface. The first and second surfaces are flat surfaces. The prism is a monolithic prism-mask, where an optical path passes through the system and exits the first surface of the prism through the mask layer. The system may include a layer disposed between the mask and resist layers. The mask layer of the prism may pattern the resist layer without an isolated mask layer.

Prism-mask for angled patterning applications

Growing community of inventors

Phoenix, AZ, United States of America

Leonel R Arana