Nxp B.v.

Leonardus Antonius Elisabeth Van Gemert

Tonny Kamphuis

Caroline Catharina Maria Beelen-Hendrikx

Christian Zenz

Roelf Anco Jacob Groenhuis

Hartmut Buenning

Jetse De Witte

Franciscus Henrikus Martinus Swartjes

Sascha Moeller

Jan Gulpen

Emil Casey Israel

Coenraad Cornelis Tak

Marten Oldsen

Hendrik Bouman

Rintje Van Der Meulen

Consistent with example embodiments, a wafer substrate undergoes processing in which a resilient material is applied to the front-side and back-side surfaces of the wafer substrate. By defining trenches in saw lanes between active device die, additional resilient material may be placed therein. In an example embodiment, after the active device die are separated into individual product devices, the resulting product device has coverage on the front-side surface, back-side surface, and the four vertical faces of the encapsulated active device die. The front-side surface has exposed contact areas so that the product device may be attached to an end user's system circuit board. Further, the resilient coating protects the encapsulated active device die from damage during assembly.

Reduction of defects in wafer level chip scale package (WLCSP) devices

Consistent with an example embodiment, a semiconductor device comprises a device die having bond pads providing connection to device die circuitry and a QFN half-etched lead frame with a package boundary; the QFN half-etched lead frame has a top-side surface and an under-side surface. The QFN half-etched lead frame includes a sub-structure of I/O terminals and a die attach area, the die attach area facilitating device die attachment thereon and the terminal I/O terminals providing connection to the device die bond pads and additional terminals located about the corners of the sub-structure. An envelope of molding compound encapsulates the device die mounted on the top-side surface of the QFN half-etched lead frame. A RF (radio-frequency) shield layer is on the envelope of the molding compound, the RF shield electrically connected to the additional terminals via conductive connections defined in corresponding locations on the envelope of the molding compound.

Shielded QFN package and method of making

Consistent with an example embodiment, there is a method for preparing an integrated circuit (IC) device having enhanced heat dissipation. The method comprises providing a lead frame array, of a first thickness, with a plurality of die placement areas each die placement area with bond pad landings, the bond bad landings situated about a die placement area on one or multiple sides, the bond pad landings having upper surfaces and opposite lower surfaces, placing a heat sink assembly of a second thickness, having at least two mounting tabs of the first thickness, in each die placement area and attaching the at least two mounting tabs onto corresponding bond pad landings serving as anchor pads, die bonding a device die on the heat sink device assembly, conductively bonding device die bond pads to corresponding bond pad landings, and encapsulating the wire bonded device die, heat sink assembly and lead frame array in a molding compound.

Heatsink very-thin quad flat no-leads (HVQFN) package

Reducing defects in wafer level chip scale package (WLCSP) devices

One example embodiment discloses a chip having a chip area, wherein the chip area includes: an overhang area; a rigid coupling area, having a set of rigid coupling points, located on one side of the overhang area; and a flexible coupling area, having a set of flexible coupling points, located on a side of the overhang area opposite to the a rigid coupling area. Another example embodiment discloses a method for fabricating a die interconnect, comprising: fabricating a rigid coupler area, having a set of rigid coupler points, within a chip having a chip area; defining an overhang area within the chip area and abutted to the rigid coupler area; and fabricating a flexible coupler area, having a set of flexible coupler points, within the chip area abutted to a side of the overhang area opposite to the rigid coupler area.

Die interconnect

In an example embodiment, an integrated circuit (IC) comprises a device die having a top-side surface and an under-side surface, the top-side surface having bond pads connected to active circuit elements, the under-side surface having a conductive surface. A first set of lead frame clips having upper portions and lower portions, are solder-anchored, on the upper portions, to a first set of bond pads; the lower portions are flush with the conductive surface. Wires are bonded to an additional set of bond pads opposite the first set of bond pads and to lower lead frame portions of a second set of lead frame clips opposite the first set of lead frame clips; the lower lead frame portions of the second set of lead frame clips are flush with the conductive surface. The device is encapsulated in a molding compound leaving exposed the conductive surface and underside surfaces of the first and second sets of the lead frame portions.

Exposed die clip bond power package

Consistent with an example embodiment, there is a semiconductor device, with an active device having a front-side surface and a backside surface; the semiconductor device of an overall thickness, comprises an active device with circuitry defined on the front-side surface, the front-side surface having an area. The back-side of the active device has recesses f a partial depth of the active device thickness and a width of about the partial depth, the recesses surrounding the active device at vertical edges. There is a protective layer of a thickness on to the backside surface of the active device, the protective material having an area greater than the first area and having a stand-off distance. The vertical edges have the protective layer filling the recesses flush with the vertical edges. A stand-off distance of the protective material is a function of the semiconductor device thickness and the tangent of an angle (&#x3b8;) of tooling impact upon a vertical face the semiconductor device.

Using a double-cut for mechanical protection of a wafer-level chip scale package (WLCSP)

Consistent with an example embodiment, there is a method for assembling a wafer level chip scale processed (WLCSP) wafer; The wafer has a topside surface and an back-side surface, and a plurality of device die having electrical contacts on the topside surface. The method comprises back-grinding, to a thickness, the back-side surface the wafer. A protective layer of a thickness is molded onto the backside of the wafer. The wafer is mounted onto a sawing foil; along saw lanes of the plurality of device die, the wafer is sawed, the sawing occurring with a blade of a first kerf and to a depth of the thickness of the back-ground wafer. Again, the wafer is sawed along the saw lanes of the plurality of device die, the sawing occurring with a blade of a second kerf, the second kerf narrower than the first kerf, and sawing to a depth of the thickness of the protective layer. The plurality of device die are separated into individual device die. Each individual device die has a protective layer on the back-side, the protective layer having a stand-off distance from a vertical edge of the individual device die.

Protection of a wafer-level chip scale package (WLCSP)

Consistent with an example embodiment, there is semiconductor device assembled to resist mechanical damage. The semiconductor device comprises an active circuit defined on a top surface, contact areas providing electrical connection to the active circuit. There is a pedestal structure upon which the active circuit is mounted on an opposite bottom surface; the pedestal structure has an area smaller than the area of the active device. An encapsulation, consisting of a molding compound, surrounds the sides and the underside of the active device and it surrounds the contact areas. The encapsulation provides a resilient surface protecting the active device from mechanical damage. A feature of the embodiment is that the contact areas may have solder bumps defined thereon.

Encapsulated wafer-level chip scale (WLSCP) pedestal packaging

Presented is an integrated circuit packaged at the wafer level wafer (also referred to as a wafer level chip scale package, WLCSP), and a method of manufacturing the same. The WLCSP comprises a die having an electrically conductive redistribution layer, RDL, formed above the upper surface of the die, the RDL defining a signal routing circuit. The method comprises the steps of: depositing the electrically conductive RDL so as to form an electrically conductive ring surrounding the signal routing circuit; and coating the side and lower surfaces of the die with an electrically conductive shielding material.

Growing community of inventors

Nijmegen, Netherlands

Leonardus Antonius Elisabeth Van Gemert