Synopsys, Inc.

Leonardos J Van Bokhoven

Balkrishna R Rashingkar

Peiqing Zou

Systems and methods are described for creating a netlist abstraction that provides full-chip context for performing circuit design floorplanning. The netlist abstraction can include a top-level netlist abstraction that corresponds to the top-level portion of the netlist, and a physical block netlist abstraction for each physical block in the circuit design. Each physical block netlist abstraction can retain macros that are in the physical block.

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Waalre, Netherlands

Leonardos J Van Bokhoven