Nvidia Corporation

Lsi Logic Corporation

Leonardo Vainsencher

Cahide Kiris

Harikrishna Madadi Reddy

Wei Sun

Lefan Zhong

Visalakshi Vaduganathan

Ram Prabhakar

Nishit Kumar

A dynamic AC prediction technique is implemented in a data partition mode which automatically disables AC prediction for encoding the current macroblock in the next packet when packet overflow occurs. Otherwise, when there is no overflow, AC prediction remains enabled to maintain compression efficiency. More particularly, in the preferred embodiment, a determination is first made whether a macroblock causes a packet overflow if it is encoded in the current packet. If so, a new packet is initiated into which the macroblock is encoded without AC prediction as the first macroblock. Otherwise, the macroblock with AC prediction remains in the current packet and a new macroblock is encoded.

Dynamic packet size control for MPEG-4 data partition mode

Systems and methods are disclosed to detect and correct errors in a flash memory using an error correction cache that provides error correction information by accessing data from a physical block number (PBN) of the flash memory; and if a data error occurred, applying error correction information stored in the cache corresponding to the accessed PBN to correct the data error.

Error correction for flash memory

Systems and methods are disclosed to perform fast discrete cosine transform (DCT) by computing the DCT in five stages using three coefficients, and scaling the outputs using a plurality of scaling coefficients.

Forward discrete cosine transform engine

Error correction cache for flash memory

Systems and methods are disclosed to detect and correct errors in a flash memory by detecting in hardware an error based on one of three selectable modes of error detection and correction; and correcting the error by executing error correction software corresponding to the selected mode of error detection and correction.

A highly integrated, single chip computer system having not only a central-processing unit (CPU) but also specialized coprocessors. The specialized coprocessors, for example, enable the single chip computer system to be reasonably sized, yet perform high quality video (e.g., MPEG-2) and graphics operations (e.g., three-dimensional graphics). The single chip computer system offers improved performance of video and graphics operations, resource scheduling and security. The improved security offered by the single chip computer system enables program code or data stored external to the single chip computer system to be encrypted so as to hinder unauthorized access, while internal to the single chip computer system the program code or data is decrypted. The single chip computer system is particularly suitable for video game consoles having high quality graphics and/or video, digital video disk (DVD) players, and set-top boxes.

Single chip computer having integrated MPEG and graphical processors

An MPEG decoder system and method for decoding frames of a video sequence. The MPEG decoder includes motion compensation logic which analyzes motion vectors in an encoded frame of the MPEG stream and uses prior decoded reference blocks to recreate the data encoded by the motion vector. The MPEG decoder stores reference block data according to a novel skewed tile arrangement to minimize the maximum number of page crossings required in retrieving this data from the memory.

System and method for performing motion compensation using a skewed tile

The present invention addresses the problem of describing an arbitrary object (up to user-defined limits) given a set of triangles with vertex normals describing the object. A novel method of successively merging traingles into larger and larger patches to compute a set of 'as-few-as-possible' Bezier patches is presented. This method is not only applicable to arbitrary objects, but also aims at producing as few patches as possible depending on the geometry of the input object. Also presented are methods to enforce C.sup.0 - and C.sup.1 -continuity between a pair of patches B.sub.L (s,t) and B.sub.R (s,t), placed arbitrarily. The methods perturb the appropnate control points to achieve geometric continuities. For C.sup.0 -continuity the area of the hole between the patches is minimized by formulating the area as a series of linear programs, where the continuity has to be enforced across the adjacent boundary curves B.sub.L (1,t) and B.sub.R (0,t). Similarly, to enforce C.sup.1 -continuity the hole-area in tangential space is minimized.

System and method for parametric surface representation from polygonal

A method for efficient, high quality rendering of a surface patch. The method tests a surface patch for flatness, and if the surface patch is not flat, the method divides the surface patch into a left surface patch and a right surface patch. Otherwise if the surface patch is flat, the method converts the surface patch into triangles. This method can be implemented to operate recursively, thereby ensuring that all portions of the patch are eventually converted into triangles when the portions become small enough to satisfy the flatness condition. A patch tests as flat only if all curves which form the patch do not deviate from straight lines by more than a predetermined tolerance. The division is efficiently performed by determining (i) left patch control points for a first portion of all curves along one axis of the surface patch, and (ii) right patch control points for a second portion of all curves along said axis of the surface patch. The axis of division preferably alternates, so that the dividing is done along a second axis if patch is not flat along the second axis and a preceding division occurred along a first axis. The method also includes tests for backfaced orientation of the patch and external location of the patch. The patch is discarded if it faces away from the viewpoint or does not appear inside the viewing region.

Growing community of inventors

San Jose, CA, United States of America

Leonardo Vainsencher