Performance Semiconductor Corporation

Sun Microsystems, Inc.

Leonardo Sandman

Yeshayahu Mor

Yeshayahu Schatzberger

Daniel D Gonsalves

Lance E Terry

Paul D Welch

Kia-Pin A May

The disclosed invention relates to the employment of a spacer element for mounting, aligning and spacing a computer chip relative to a PCB. The spacer element is formed and dimensioned to engage the chip in a manner to assure that the pins of the chip are properly aligned relative to openings in the PCB and to assure that the chip is centered and maintained parallel to the PCB and each of its pins maintained equal distance from the underneath side of the PCB during the wave soldering process for electrically connecting the chip and PCB.

Computer chip spacer element

Normalization and scaling operations are performed by the use of the fast shifter of a micrprocessor operating in response to the system clock, rather than in response to microinstructions. By local control of the fast shifter, multiple shift steps essential to normalization and scaling operations are performed at a much faster rate than possible in the prior art wherein each bit shift must be controlled by a single microinstruction, and without the heavy cost in integrated circuit chip area that a barrel shifter requires. When a scaling or normalization operation is to be performed, the system clock is gated to the fast shifter, thus allowing the shift operation to take place in response to the gated clock. Simultaneously, when the shifting operation is taking place, a WAIT signal is provided, telling the microprocessor to postpone action on the next microinstruction until the shifter operation has been completed. The fast shifter is capable of performing either single or double bit shifts to either the right or left, as desired. The fast shifter is also use to implement the parametric shift instructions in the microprocessor instruction set, providing a similar performance enhancement to these operations.

Fast shifter method and structure

A microprocessor for processing operand bits has a 16 bit primary arithmetic logic unit (ALU) and shifter and a 24 bit auxiliary ALU and shifter operating in conjunction with the primary ALU. Some of the total number of operand bits are loaded into the auxiliary ALU and processed therein in advance of the processing of bits in the primary ALU. This permits a 16 bit microprocessor to perform operations with 32 bit or 48 bit operands without any performance penalties and without requiring an increase in the microcode utilized. The invention is particularly useful and valuable in such operations as multiplication and division operations, that are of a highly repetitive nature, and for all floating point operations.

Microprocessor system with extended arithmetic logic unit

Comparison of two floating point numbers is performed using a unique algorithm, which in one embodiment is implemented very efficiently in hardware, resulting in a very significant improvement in the floating point comparison execution time. In order to perform a floating point comparison, the exponents of the two numbers to be compared are subtracted. In many cases, the exponents are not equal, and simply determining which exponent is larger, combined with the signs of the mantissas of each of the floating point numbers being compared, is sufficient to determine which of the two floating point numbers being compared is larger. Alternatively, if the exponents of the two floating point numbers being compared are equal, the mantissas may be subtracted without need for shifting mantissas in order to equalize the exponents. In this manner, the floating point comparison operation is greatly simplified and the time consuming multiple shift operation is avoided, thereby vastly reducing the amount of time required to perform the floating point comparison, and thereby increasing the overall speed of operation of the microprocessor.

Method and structure for performing floating point comparison

A computer is sped up by reducing significantly the time necessary for the computer to detect and respond to an overflow following an ALU operation of a type which generates an overflow. This is done by assuring the next instruction in sequence is the one to be executed and in parallel detecting the occurrence of an overflow as the result of an implementation of a selected instruction and then producing a flag in response to the overflow. The flag is detected, and selected portions of the computer are disabled to inhibit any change in state within the computer following the generation of the overflow. An interrrupt sequence is then implemented to correct the output of the instruction which generated the overflow to compensate for the overflow. The next following instruction is then implemented after completion of the interrupt routine. Consequently, a delay following each instruction of a type which can generate an overflow is avoided unless an overflow condition actually exists because should an overflow not exist the computer automatically implements the next correct following instruction. In an alternative embodiment, an ALU operation capable of producing a branch signal is followed by the most likely microinstruction to occur. Should, however, the ALU operation indicate a branch, selected components of the computer are disabled to inhibit any change in state within the computer following the generation of the branch signal. An alternative microinstruction is then implemented in response to the branch signal. A selected sequence of microinstructions is then implemented following the completion of the alternative microinstruction. Consequently, a delay following each instruction of a type which can generate a branch is avoided unless a branch signal actually is generated.

On-line overflow response system and ALU branching structure

A microcoded data processing system utilizes common microcode execution routines for both register-to-register operations and memory-to-register operations. The system includes a memory data register for storing an operand for use in a memory-to-register operation, a pair of address registers for containing the addresses of the registers to be involved in the execution of register-to-register instructions, and circuitry responsive to generation of an instruction indicating a memory-to-register operation for generating the address of the memory data register from one of the address registers, whereby the register-to-register operations and the memory-to-register operations can share common execution routines without any performance time penalty or any increase in required microcode. The system also provides for the simultaneous generation of the addresses of all registers to be employed in instructions involving multipart operands.

Growing community of inventors

Cupertino, CA, United States of America

Leonardo Sandman