Avaya Technology LLC

Knowles Electronics, Inc.

Audience, Inc.

Octel Communications Corporation

Leonardo Rub

Peter Hunt

Kamil A Grajski

Susannah Albright

Dana C Massie

Brian D Clark

Samuel Charles Dicker

David P Rossum

Jean Laroche

A multi-core audio processor includes a data protocol interface configured to receive a stream of audio data, a plurality of data processing cores including a single sample processing core and a block data processing core, an audio fabric block configured to route samples of the stream between the data protocol interface and the plurality of data processing cores. The single sample processing core includes an execution unit configured to execute one or more low latency instructions for performing computations for the samples.

Multi-core audio processor with low-latency sample processing core

An integrated circuit for processing audio signals from a microphone assembly, combinations thereof and methods therefor, including a multi-issue processor configured to execute multiple instructions concurrently and connectable to a memory with a plurality of locations each represented by a corresponding index. Bit-reversal is performed on a sequence of audio data bits stored in memory by concurrently performing a load or store operation related to a first index and determining whether to perform a load operation for a second index.

Audio signal circuit with in-place bit-reversal

Systems and methods for multiplying a sparse matrix by a vector using a single instruction multiple data (SIMD) architecture are provided. An example method includes sorting rows of the sparse matrix by a number of non-zero elements in the rows to generate sorted rows. The sorted rows are split to generate groups of the sorted rows. The number of rows in each group of the sorted rows is equal to the number of rows updated in parallel. The method allows for packing the sorted rows in each of the groups to generate packed rows. Each of the packed rows within the same group has the same length. Per clock cycle, C elements of the packed rows and data for selecting elements of the vector are provided to computational units in the SIMD architecture, where C is the number of computational units.

Sparse matrix vector multiplication

Arithmetic units and methods for floating point processing are provided. In exemplary embodiments, data paths to and from multiple multipliers and adders are flexibly combined through crossbars and alignment units to allow a wide range of mathematical operations, including affine and SIMD operations. The micro-architecture for a high-performance flexible vector floating point arithmetic unit is provided, which can perform a single-cycle throughput complex multiply-and-accumulate operation, as well as a Fast Fourier Transform (radix-2 decimation-in-time) Butterfly operation.

Multi-function floating point unit

Digital methods and systems for signal processing and filtering are provided. The methods and corresponding systems provide asynchronous conversion of sampling rate frequencies and utilize advanced multistage phasor filters for converting an input signal having a first sampling rate into an output signal sampled in an arbitrary sequence of sampling times. The conversion process provides a sequence of sets of complex numbers representing a filtered version of the input signal. More specifically, the conversion process includes the calculation of values of the output signal by multiplying (e.g., scaling) the sets of complex numbers by a corresponding set of complex phasors, the complex phasors corresponding to the timing of the arbitrary time sequence to obtain a corresponding set of real results with the value of the output signal being the sum of the real results.

Sample rate conversion using infinite impulse response filters

A system and method for speech-responsive voice messaging, in which a Speech-Responsive Voice Messaging System (SRVMS) preferably provides a hierarchically-simple speech user interface (UI) that enables subscribers to use speech to specify commands such as mailboxes, passwords, and digits. The SRVMS generates and evaluates candidate results. The SRVMS invokes a speech UI navigation operation or a voice messaging operation according to the outcome of the evaluation of the candidate results. In the preferred embodiment, the SRVMS determines whether the candidate results are good, questionable, or bad; and whether two or more candidate results are ambiguous due to a likelihood that each such result could be a valid command. If the candidate results are questionable or ambiguous, an ambiguity resolution UI prompts the subscriber to confirm whether the best candidate result is what the subscriber intended. In response to repeated speech recognition failures, the SRVMS transfers the subscriber to a Dual Tone Multi Frequency (DTMF) UI. Transfer to the DTMF UI is also performed in response to detection of predetermined DTMF signals issued by the subscriber while the speech UI is in context. The SRVMS provides a logging unit and a reporting unit which operate in parallel with the speech UI, in a manner that is transparent to subscribers. The logging unit directs the selective logging of subscriber utterances, and the reporting unit selectively generates and maintains system performance statistics on multiple detail levels.

Growing community of inventors

Sunnyvale, CA, United States of America

Leonardo Rub