Robert Boschgmbh

Leonardo Luiz Ecco

Andre Guntoro

Norbert Wehn

Taha Ibrahim Ibrahim Soliman

Chirag Sudarshan

Christian Weis

Dieter Thoss

Jo Pletinckx

Sebastian Vogel

Christoph Schorn

A method for operating a hardware platform for the inference calculation of a layered neural network. In the method: a first portion of input data which are required for the inference calculation of a first layer of the neural network and redundancy information relating to the input data are read in from an external working memory into an internal working memory of the computing unit; the integrity of the input data is checked based on the redundancy information; in response to the input data here being identified as error-free, the computing unit carries out at least part of the first-layer inference calculation for the input data to obtain a work result; redundancy information for the work result is determined, based which the integrity of the work result can be verified; the work result and the redundancy information are written to the external working memory.

Inference calculation for neural networks with protection against memory errors

A memory device comprising a plurality of memory cells situated in a first cell field, multiple first bit lines, each respectively connected to multiple memory cells of the first cell field to enable access to the memory cells via the bit line, and multiple sense amplifier pairs which respectively comprise a first and a second sense amplifier. Each first bit line is assigned to a sense amplifier pair, each first bit line being connected to a respective first semiconductor switch element, through which the bit line is electroconductively connectible to and insulatable from the first sense amplifier of the sense amplifier pair, to which the bit line is assigned. Each first bit line is connected to a respective second semiconductor switch element, through which the bit line is electroconductively connectible to and insulatable from the second sense amplifier of the sense amplifier pair, to which the bit line is assigned.

Memory device and method for performing consecutive memory accesses

A memory device comprising a cell field having memory cells, N bit lines, which are respectively connected to at least one of the memory cells of the cell field, N being a whole number greater than one, N sense amplifiers; a bit shift circuit, which has S switch element rows, S being a whole number greater than one and a row number in the range from zero to S−1 being assignable to each switch element row. Each switch element row includes at least one semiconductor switch element connected to one of the bit lines and one of the sense amplifiers. Switch elements of each row connect all bit lines, whose bit line number is smaller than or equal to N minus the row number, to sense amplifiers, so that the respective sense amplifier number is equal to the respective bit line number plus the row number.

Memory device and method for shifting memory values

A method for checking data in a storage unit of a system on a chip; a monitoring unit, which may be activated or deactivated by the system on a chip, being implemented in the system on a chip. When it is activated, the monitoring unit storing error correction codes for executing error correction methods, in the storage unit, such that, for a predefined number of data blocks of the storage unit, in each instance, a data block including an associated error correction code is stored. When access to data in the storage unit is intended to take place, the monitoring unit addresses the respective data and an associated error correction code and checks the addressed data prior to the respective access, using the addressed error correction code, and correcting them when required.

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Stuttgart, Germany

Leonardo Luiz Ecco