University of Arkansas

Leonard W Schaper

Ajay Prabhakar Malshe

William David Brown

Hameed A Naseem

Chad O'Neal

James Patrick Parkerson

John H Glezen

A structure and process for packaging RF MEMS and other devices employs a substrate of silicon, for example, and a cap of glass, for example, having cavities to receive the devices. MEMS or other devices are supported on an upper surface of the substrate, into which metal-filled blind vias are formed. The cap is attached to the substrate, so as to enclose designated MEMS or other devices in the cavities. The substrate is then thinned so as to expose the metal of the vias at a lower surface of the substrate. Electrical connecting elements such as solder balls are then applied to the metal of the vias. The resultant composite substrate is then divided to provide individual packaged devices.

Method of packaging RF MEMS

A thin-film RC circuit element suitable for a transmission line termination circuit is prepared by a process wherein

RC terminator and production method therefor

A capacitive structure is made with thin film capacitor plates substantially surrounding an opening cavity for accommodating a chip. The capacitive structure includes at least one capacitor and is mounted around the periphery of a ball grid array (BGA) having a flip chip in the opening. The capacitive structure provides a high capacitance with a low parasitic inductance.

Decoupling capacitor for integrated circuit package and electrical components using the decoupling capacitor and associated methods

An interconnected mesh plane system includes at least a pair of adjacent metal layers separated by dielectric, each layer having a plurality of spaced power, ground, and signal conductors extending in the same direction, with the conductors of one layer of the pair transverse to the conductors of the other layer, and with conductors of one layer connected to corresponding conductors of the other layer. The width of at least one signal conductor is increased to reduce signal loss, and the width of spaces between such a signal conductor and adjacent power and/or ground conductors is increased to provide a predetermined desired characteristic impedance of a transmission line that includes such a signal conductor.

Apparatus and method for providing low-loss transmission lines in interconnected mesh plane systems

Surface applied passive devices for use on electronic circuit boards are formed by applying layers of conductive, insulating, and other material to a thin polymer film carrier. The surface applied passives are thin enough to fit underneath standard integrated circuit packages in order to conserve space on the circuit board. Resistors, capacitors, inductors and other passive circuits may be formed on thin polymer films, less than 8 mils thick. This significantly aids in conserving space on an electronic circuit board.

Surface applied passives

A capacitor having a floating plate-shaped electrode, at least two patterned plate electrodes overlying the floating plate-shaped electrode, and a dielectric layer therebetween. The resulting structure exhibits high two-port insertion loss even at frequencies as high as 10 GHz. Notably, the capacitor exhibits an insertion loss of more than &minus;40 dB over a range from 1 GHz to 10 GHz.

Method of making capacitor with extremely wide band low impedance

An electrical interconnection medium is provided having first and second overlying interconnection layers. Each interconnection layer includes parallel conductors, and the conductors of the first and second interconnection layers are oriented orthogonally to each other. The conductors can be interconnected to form at least two electrical planes, with the conductors of the electrical planes being substantially interdigitated on each interconnection layer, portions of each plane appearing on both layers. The interconnection medium advantageously is employed as a multichip module. A method of designing such an MCM includes providing arranged conductive regions in a spaced manner, cutting selected sections to form signal conductor paths, and then filling spaces between like power and ground conductors. Another embodiment provides arranging touching conductive regions, defining signal path areas along uniformly-spaced touching borders, and then carving away conductive material to form desirably positioned and spaced power, ground and signal conductors.

Electronic interconnection medium having offset electrical mesh plane

Multichip module and method of forming same

A capacitor exhibits high two-port insertion loss even at frequencies as high as 10 GHz. Notably, the capacitor exhibits an insertion loss of more than &minus;40 dB over a range from 1 GHz to 10 GHz and no inductive resonance below a frequency of at least 1 GHz.

Floating plate capacitor with extremely wide band low impedance

A capacitor having a floating plate-shaped electrode, at least two patterned plate electrodes overlying the floating plate-shaped electrode, and a dielectric layer therebetween. The resulting structure exhibits high two-port insertion loss even at frequencies as high as 10 GHz. Notably, the capacitor exhibits an insertion loss of more than -40 dB over a range from 1 GHz to 10 GHz.

Disclosed is an electroplating method and products made therefrom, which in one embodiment includes using a current density J.sub.O, to form a conductive metal layer having a surface roughness no greater than the surface roughness of the underlying member. In another embodiment of electroplating a substrate surface having peaks and valleys, the method includes electroplating a conductive metal onto the peaks to cover the peaks with the conductive metal, and into the valleys to substantially fill the valleys with the conductive metal.

Method of electroplating a substrate, and products made thereby

Disclosed is a method of planarizing a diamond film which generally includes orifices in the surface. The method includes first polishing the diamond film surface to reduce the surface roughness. Next, a filler material is applied to the surface of the film to fill the orifices in the film. Finally, the film is polished to remove excess filler material and expose the diamond film surface. Also disclosed are planarized diamond films diamond substrate having a polished surface of both diamond and filler material and a variation in thickness of less than 8 percent.

Method of planarizing polycrystalline diamonds, planarized

An electrical interconnection medium having first and second overlying interconnection layers, each interconnection layer including parallel conductors, the conductors of the first and second interconnection layers being oriented orthogonal to each other, the conductors being interconnected so as to form at least two electrical planes, the conductors of the electrical planes being substantially interdigitated on each interconnection layer, portions of each plane appearing on both layers. The interconnection medium advantageously is employed as a multichip module.

Growing community of inventors

Fayetteville, AR, United States of America

Leonard W Schaper