Intel Corporation

Leonard W Cross

Ali S Oztaskin

Eric Dahlen

Douglas Raymond Moran

Raman Nayyar

David R Jackson

Peter B Bloch

John L Allen

Bill A Munson

Robert A Jacobs

Roger L Traylor

David W Bogardus

Patrick F Doyle

Edward Paul Wallace

Roger Noar

According to an embodiment of the invention, systems, apparatus and methods are disclosed for providing bimodal voltage references for use in differential signaling between components or devices. According to an embodiment, a switchable power supply is used to produce at least one of two or more supply voltages based on the value of a selection signal received by the switchable power supply. This selection signal is also used by at least one of the elements to switch between a reference voltage produced by another device and a reference voltage derived from the supply voltage. In certain embodiments, the reference voltage derived from the power supply and the selection via a multiplexing circuit is contained within one of the devices (e.g., a chip), which provides certain design and cost advantages.

Method and apparatus for providing bimodal voltage references for differential signaling

A method and apparatus are provided for performing address translation in an input/output (I/O) expansion bridge. The I/O expansion bridge includes a first interface unit, a second interface unit, and an address translation unit. The first interface unit is configured to be coupled to a system memory and I/O controller through one or more I/O ports. The first interface unit enables data transfers over the one or more I/O ports to or from the main memory of a computer system. The second interface unit provides bus control signals and addresses to enable data transfers over a bus to or from a peripheral device. The address translation unit is coupled to the first interface unit and the second interface unit. The address translation unit translates addresses associated with transactions received on the second interface by accessing a local memory containing physical addresses of pages in the main memory of the computer system.

Graphics address relocation table (GART) stored entirely in a local memory of an input/output expansion bridge for input/output (I/O) address translation

Graphics address relocation table (GART) stored entirely in a local memory of an expansion bridge for address translation

According to the invention, systems, apparatus and methods are disclosed for providing bimodal voltage references for use in differential signaling between components or devices. In an embodiment, a switchable power supply is used to produce at least one of two or more supply voltages based on the value of a selection signal received by the switchable power supply. This selection signal is also used by at least one of the elements to switch between a reference voltage produced by another device and a reference voltage derived from the supply voltage. In certain embodiments, the reference voltage derived from the power supply and the selection via a multiplexing circuit is contained within one of the devices (e.g., a chip), which provides certain design and cost advantages.

An apparatus for managing power in an electronic device that receives the power from a bus is described. The apparatus comprises a clock enable circuit that disables a clock that generates nominal clock frequencies derived from raw frequencies output by an oscillator upon receiving a first signal. A time-wise independent time reference circuit is coupled to the clock enable circuit. The time-wise independent time reference circuit sends the first signal to the clock enable circuit a first predetermined period of time after receiving a signal to enter into a suspend state.

Method and apparatus for supporting power conservation operation modes

A method and device is provided for controlling access to a resource by a bus master over a bus coupling the bus master to the resource. The resource includes an intelligent component that controls the operation of the resource. A series of packets is transmitted over the bus between the bus master and the resource, at a transmission speed controlled by the bus master. A request/response logic in the resource controllably throttles transmissions of the packets at the resource, at specified time intervals. Each of the time intervals is set at a time period to assure sufficient time for the intelligent component to complete processing tasks contained in the packets.

Programmable and adaptive resource allocation device and resource use

A method and apparatus for storing data values received within respective cycle periods of a clock signal are disclosed. Data values are alternately stored in first and second data hold registers and then output by each data hold register for a time greater than a cycle period of the clock signal. Address values at which the incoming data values are to be written are alternately stored in first and second address hold registers. Data stored in the first data hold register is written to a latch-based memory element in a first memory bank indicated by an address value stored in the first address hold register. Data stored in the second data hold register is written to a latch-based memory element in a second memory bank indicated by an address value stored in the second address hold register.

Method and apparatus for storing data in a sequentially written memory

A method and apparatus for draining video data from a planarized video buffer in a video camera. The method includes the steps of reading a first sequence of video data from a first plane of the planarized image buffer starting at a buffer address indicated by a first pointer, and then reading a second sequence of video data from a second plane of the planarized image buffer starting at a buffer address indicated by a second read pointer. The apparatus includes an address generation unit and a sequence counter. The address generation unit includes a number of read pointers each configured to indicate a memory location within a different data plane of a video buffer. The address unit is configured to address a sequence of memory locations in a video buffer starting at a location indicated by an active one of the read pointers. The sequence counter is configured to detect when a final memory location of the sequence of memory locations has been addressed by the address generation unit and, in response, to select a different one of the read pointers to be the active read pointer.

Method and apparatus for draining video data from a planarized video

Briefly, in accordance with one embodiment, an integrated circuit includes: electronic circuitry for transferring digital data signals along a digital data signal path between different clock timing domains. The clock timing domains have a common higher frequency source clock. A first clock timing domain clock signal has a relatively fixed phase and a second clock timing domain clock signal has a relatively varying phase. The electronic circuitry includes delay elements in clock signal paths associated with the digital data signal path so that along the digital data signal path, clock signals in different clock timing domains are respectively staggered for a relatively short time compared with a given cycle of the source clock. The electronic circuitry further includes a digital data signal path including a data value retention element to delay the transfer of digital data signals between different clock timing domains at selected times.

Method and apparatus for transferring signals between multiple clock

A programmable digital filter. The digital filter detects a predefined pattern over a programmably variable duration. The filter includes an interval register which is coupled to receive an interval count. A sample register is coupled to receive a plurality of samples of an input signal which is sampled at an interval determined by the interval count. A plurality of pattern matching circuits generate a pattern match output if the plurality of samples matches one of a plurality of predetermined patterns, and a state logic circuit generates a signal if a new match is found. The pattern matching circuits may be stable high and stable low test circuits which cooperate to determine if all of the plurality of samples are of a consistent logic value.

Programmable digital filter for stable interval detection

A video scaling engine for scaling video data over a plurality of clock cycles is disclosed. In a first clock cycle of the plurality of clock cycles, a multiplier of the video scaling engine multiplies an input pixel by a coefficient indicated by a coefficient select signal to generate a first product. The first product is stored in an accumulator of the video scaling engine. In a second clock cycle of the plurality of clock cycles, the multiplier multiplies another input pixel by a coefficient indicated by another coefficient select signal to generate a second product. The second product is added to the contents of the accumulator to produce a sum including the first and second products. The sum including the first and second products is stored in the accumulator and then divided by a value based on at least one of the coefficients to produce a scaled output pixel.

Digital video scaling engine

The present invention relates to a method and apparatus for asynchronously transferring data from a first synchronous sequential logic circuit which derives its clock source from a first clock to a second synchronous sequential logic circuit which derives its clock source from a second clock, whereby metastability of the second synchronous sequential logic circuit is avoided. The invention comprises a data path and a control path; a data synchronizer coupled to the data path for synchronizing data signals; a control synchronizer coupled to the control path for synchronizing control signals; a register coupled in parallel to the data path for storing valid data output from the data synchronizer; a multiplexor having one input coupled to the data path, another input coupled to the register, a selector input coupled to the control path for selecting between receiving as input synchronized data signals or the contents of the register, and an output for transmitting valid data. If metastability is unlikely, the control signal is deasserted causing the multiplexor to select the synchronized data as input. If metastability is likely, the synchronized control signal is asserted causing the multiplexor to select the register as input. The basic test is whether to accept the new state of the data signal or wait and use the old state currently maintained in the register, until such time as the likelihood of metastability has passed, as indicated by the synchronized control signal.

Method of delivering stable data across an asynchronous interface

A programmable and testable memory address decoder for a computer system where a static random access memory device is used to store memory configuration information. The computer system includes a processor which is coupled to the memory address decoder via data and address lines. The memory address decoder includes an SRAM for storing a memory map which associates memory attributes with memory ranges or blocks of memory. The memory attributes include: memory residence, caching, write protection of memory ranges, and the decoding of other memory modules. The present invention also includes control logic, a read-back register, and a mode register for controlling the loading and read back verification of the SRAM. The control logic operates the memory address decoder in one of four modes. These modes include: 1) power-up mode, 2) programming mode, 3) read back mode, and 4) normal operation mode. One of these modes is selected by loading the mode register with a value corresponding to the desired mode. A default power up mode is entered after power is first applied to the computer system. When the processor specifies a programming mode, the processor may write data directly into the SRAM. When the processor specifies the read back mode, the contents of the SRAM may be read back by the processor through the read back register. A normal mode may be entered in order to enable access to system memory (DRAM) with memory attribute information.

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Portland, OR, United States of America

Leonard W Cross