Cypress Semiconductor Corporation

Leonard Vasile Gitlan

Ryan Tasuo Hirose

Bogdan I Georgescu

Fredrick B Jenne

Igor G Kouznetsov

Cristinel Zonte

Paul Fredrick Ruths

James Paul Myers

Vijay Raghavan

Ashish Ashok Amonkar

Gary Peter Moscaluk

John W Tiede

Vijay Srinivasaraghavan

Vijay Kumar Srinivasa Raghavan

A system including a memory architecture is described. In one embodiment, the memory architecture includes an array of non-volatile memory cells, a first independently controlled voltage generation circuit, a plurality of register bits to store programmable values used by the independently controlled voltage generation circuit and a control circuit coupled to the first independently controlled voltage generation circuit. The first independently controlled voltage generation circuit is coupled to supply a positive voltage to the array during program and erase operations so that a magnitude of the positive voltage is applied across a storage note of an accessed memory cell of the array. The plurality of register bits to store programmable values used by the independently controlled voltage generation circuit to control the magnitude of the positive voltage. The control circuit controls a duration of the positive voltage. Other embodiments are also described.

Memory architecture having two independently controlled voltage pumps

A system including a memory architecture is described. In one embodiment, the memory architecture includes an array of non-volatile memory cells, a first independently controlled voltage generation circuit, a plurality of register bits to store programmable values used by the independently controlled voltage generation circuit and a control circuit coupled to the first independently controlled voltage generation circuit. The first independently controlled voltage generation circuit is coupled to supply a positive voltage to the array during program and erase operations so that a magnitude of the positive voltage is applied across a storage node of an accessed memory cell of the array. The plurality of register bits to store programmable values used by the independently controlled voltage generation circuit to control the magnitude of the positive voltage. The control circuit controls a duration of the positive voltage. Other embodiments are also described.

Systems and methods for switching between voltages are provided. One system includes an output, first and second switches coupled to the output. The system also includes a first transmission gate coupled to the first switch and a second transmission gate coupled to the second switch. One method includes receiving, at the first transmission gate, a first pair of complementary voltages and receiving, at the second transmission gate, a second pair of complementary voltages. The method further includes selecting the smallest voltage amongst both pairs of complementary voltages and outputting a third pair of complementary voltages. In one method, the first pair of complementary voltages includes a first negative voltage and a positive voltage, the second pair of complementary voltages includes a second negative voltage and the positive voltage, and the third pair of complementary voltages includes the smaller of the first and second negative voltages and the positive voltage.

Systems and methods for switching between voltages

Apparatus, systems, and methods for providing high voltage to memory devices are provided. One apparatus includes a low voltage input and a two-rail level shifting. The two-rail level shifting is configured to increase the low voltage or to decrease the low voltage to an amount that is less than or equal to a ground potential based on the amount of the low voltage. A system includes a low voltage input for receiving a voltage and a two-rail level shifting coupled to the low voltage input. The two-rail level shifting is configured to increase the voltage to a positive voltage if the voltage is equal to a ground potential and decrease the voltage to a negative voltage if the voltage is greater than the ground potential. One method includes receiving a voltage, modifying the voltage to generate one of a plurality of output voltages, and providing the output voltage to a memory device.

Systems and methods for providing high voltage to memory devices

In embodiments described herein, a memory architecture has an array of non-volatile memory cells and a pair of independently controlled voltage pumps. The pair of voltage pumps is coupled for supplying both positive and negative voltage biases to the memory array during program and erase operations, such that a sum of the magnitudes of the positive and negative voltage biases is applied across a storage node of an accessed memory cell.

A memory architecture is provided with an array of non-volatile memory cells arranged in rows and columns, and a sense amplifier coupled to at least one column within the array for sensing a data bit stored within one of the non-volatile memory cells. In order to provide accurate sensing, a reference current generator is provided and coupled to the sense amplifier. The reference current generator provides a first reference current having adjustable magnitude and adjustable slope, and a second reference current having adjustable magnitude, but constant slope. The first reference current is supplied to the sense amplifier for sensing the data bit. The second reference current is supplied to a control block for generating clock signals used to control sense amplifier timing.

Memory architecture having a reference current generator that provides two reference currents

A method of optimizing memory cell write/read is disclosed. The memory cell write/read is optimized by first reading the memory cell data using the normal mode. Next the page latch data that was used to NV (Non-Volatile) write the memory is also read back directly from the page latches. The two data are then compared to verify a successful and optimized memory cell write/read. NV writes and reads are performed with various high voltage parameters and sense amplifier reference settings to arrive at the most optimal one that gives the largest sense window for best write/read reliability. The page latch read mode is also used as a DFT (Design for Test) test mode to check for page latch functionality and page address uniqueness without having to write the memory cell. The page latch is written with logic data and read out directly using the page latch read mode to verify page functionality.

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Colorado Springs, CO, United States of America

Leonard Vasile Gitlan