International Business Machines Corporation

Leonard T Olson

Mario E Ecker

David Peter Pagnani

Ronald S Charsky

Thomas Mario Cipolla

Timothy C Reiley

Harry R Bickford

Mark F Bregman

Peter G Ledermann

Ekkehard F Miersch

William S Ebert

Richard Kachmarik

Walter V Vilkelis

Nicolaos C Arvanitakis

Vincent J BLack

Richard G Nolan

John Gow, Iii

Francis D Austin

Vincent J Black

Richard E Corley, Jr

Uh-Po E Tsou

Richard R Sloma

Michael B Brown

Richard E Corley

An optoelectronic package with direct free space optical communication between pairs of optical transmitters and receivers located on different substrate surfaces in a closely spaced stack of chip carrying substrates is disclosed. The transmitters and receivers are aligned so that a light beam from each transmitter follows an optical path toward its respective receiver. In the stack of substrates, the transmitters and receivers are mounted on the surfaces of the substrates, many of which are separated by intervening substrates. These intervening substrates have vias, holes or transparent regions, or other optical means, at locations along the optical paths connecting the transmitters and receivers. Lenses or other concentrating means, where required, are adjacent to a transmitter so that its diverging light is focused on the intended receiver. Substrates are aligned so that the light from transmitters shines through the optical means in intervening substrates to the receivers. Means for removing heat from the substrates are included.

High speed optical interconnect

Electronic device packaging structures useful for electrically interconnecting an electronic device to a substrate. The structure contains at least two metallization layers with dielectric layers between adjacent to metallization layers. The dielectric layers can have variable thickness. Beam leads can project inwardly in cantilevered fashion over a central aperture through the dielectric layers. The inner ends of the beam leads lie substantially in one plane and can be bonded to contact pads on integrated circuit electronic devices. Beam leads can project outwardly from the metallization layers over outer edges of the dielectric layers for bonding to contact pads on a substrate. Signal leads on metallization layers can be symmetrically arranged between ground and voltage leads to provide optimal impedance properties. These structures are useful for tape automated bonding applications.

Multilevel integrated circuit packaging structures

An optoelectronic assembly for providing bidirectional data transmission between fiber optic means (e.g., a pair of optical fibers) and an electrical circuit member (e.g., a printed circuit board). The assembly includes a two-part housing with first and second receptacle sections designed for accommodating a pair of optoelectronic devices. One of these devices serves as a receiver and the other a transmitter. These devices are aligned within the housing and electrically connected to a substrate member (e.g., ceramic) also positioned within the housing. The substrate provides the necessary electrical functioning and is in turn electrically connected (e.g., via conductor pins) to the described circuit member, this connection occurring through an opening within the bottom portion of the two-part housing. The assembly is designed for coupling with individual optical fiber members or, alternatively with a common duplex connector having optical fibers therein.

Optoelectronic assembly

A semiconductor chip carrier includes a plurality of distributed high frequency decoupling capacitors as an integral part of the carrier. The distributed capacitors are formed as a part of the first and second layers of metallurgy and separated by a layer of thin film dielectric material built up on a substrate. The distributed capacitors are positioned to extend from a ground pin of one of the layers of metallurgy to a plurality of mounting pads which are intergral parts of the other of the layers of metallurgy. A semiconductor chip is mounted to the mounting pads and receives electrical power and signals therethrough. The distributed capacitors decrease electrical noise associated with simultaneous switching of relatively large numbers of off-chip drivers which are electrically connected to the semiconductor chip.

Electronic package with integrated distributed decoupling capacitors

The disclosure describes a technique whereby the electrical characteristics of an electrical circuit in a package may be adjusted to a predetermined value by changes in the dielectric structure between two levels of circuitry. This adjustment in the composite dielectric structure is accomplished by changes in the electrical properties of the composite dielectric material, one level being preset to a value and the other level being adjusted by alterations of predetermined amounts that depend upon the performance desired.

Composite dielectric structure for optimizing electrical performance in

Arrangement for reducing cross talk between electrical circuit conductors wherein the conductors lie within individual parallel channels within the same plane or different parallel planes within the induced voltage or cross talk region of an energized and a quiet conductor and either converge or diverge with respect to each other. The amount of relative convergence or divergence, preferably mor than six degrees and less than 15 degrees, is that required to attenuate the magnitude of any signal induced by the activated conductor in a neighboring or quiet conductor to maintain an acceptable and desired signal-to-noise ratio.

De-coupled printed circuits

An electronic packaging structure includes a second level electronic package having at least one opening formed therein and circuitry for electrical connection to a semiconductor chip. A circuitized polyimide film chip carrier includes at least one semiconductor chip mounted on one major surface thereof and at least one decoupling capacitor mounted on an opposite surface thereof. The decoupling capacitor is electrically coupled to input/output contacts of the semiconductor chip. The carrier is then mounted on the second level electronic package so that one semiconductor chip is positioned within a respective opening and the circuitry formed on the carrier is coupled to the circuitry formed on the second level package thereby interconnecting the semiconductor chip to the electronic package.

Flexible film chip carrier with decoupling capacitors

A multi-level integrated circuit packaging system having a primary support frame, an array of secondary support frames mounted in said primary support frame and an array of single chip carriers associated with each secondary support frame. An integrated circuit is encapsulated in each single chip carrier, which may be a variety of carrier types which has an insulated wiring pattern with EC wells and delete lands. The secondary and primary support frames also have EC pads so that a change capability exists to any electrical signal path terminating on the chip.

Repairable multi-level overlay system for semiconductor device

A system for connecting a semiconductor chip carrier to a printed circuit card is described. The semiconductor chip carrier has a flexible, extendable wiring membrane attached to the bottom thereof which extends beyond the periphery of the semiconductor chip carrier and in the area beyond the periphery is provided with electrical contacts. The electrical contacts are mated to complementary contacts in a printed circuit card which is biased from the semiconductor chip carrier by electrical and thermal contact means. The membrane, inter alia, provides high density electrical contact between the semiconductor and printed circuit card. Various elements thereof and a process for forming the same are described.

High density interconnection means for chip carriers

Disclosed is a packaging structure wherein one or more integrated circuit semiconductor chips are mounted on membrane-like insulating members. The membrane-like members provide multilevel wiring and interconnection between the chip or chips and a secondary wiring structure. The packaging structure includes a module protective cap (preferably metal) and resilient means supported by said secondary wiring structure. The resilient means physically biases the semiconductor chip or chips against the module protective cap and also accommodate induced chip motion and variation. The packaging structure provides enhanced thermal, mechanical and electrical characteristics.

Growing community of inventors

Centreville, VA, United States of America

Leonard T Olson