Lucent Technologies Inc.

At&t Bell Laboratories

Applied Materials, Inc.

Agere Systems Inc.

Leonard Jay Olmer

Earl Ryan Lory

Sailesh Mansinh Merchant

Kent Rossman

Daniel Patrick Chesire

Robert E Dean

Pang-Dow Foo

Edward Paul Martin, Jr

Robert Francis Jones

Jonathon Marlon Lobbins

William Daniel Bevers

Edward P Martin

Rafael N Barba

Phillip Nguyen

Barbara D Kotzias

Karl H Kocmanek

Ronald Joseph Schutz

A process for cleaning the silicon surface of a semiconductor device material layer. The surface undergoes a pre-clean process followed by exposure to a nitrogen-containing gas. A polysilicon layer is formed on the surface in the same chamber and at about the same temperature as the cleaning and nitrogen exposing steps.

In-situ removal of surface impurities prior to arsenic-doped polysilicon deposition in the fabrication of a heterojunction bipolar transistor

Methods are provided for identifying root causes of particle issues and for developing particle-robust process recipes in plasma deposition processes. The presence of in situ particles within the substrate processing system is detected over a period of time that spans multiple distinct processing steps in the recipe. The time dependence of in situ particle levels is determined from these results. Then, the processing steps are correlated with the time dependence to identify relative particle levels with the processing steps. This information provides a direct indication of which steps result in the production of particle contaminants so that those steps may be targeted for modification in the development of particle recipes.

Method for using an in situ particle sensor for monitoring particle performance in plasma deposition processes

The present invention provides a method of determining an endpoint of a reduction reaction of a metal deposited on a semiconductor wafer. The method comprises reducing an oxidized portion of the metal by subjecting the oxidized portion to a reducing agent that forms a reduction by-product and detecting the endpoint of the reduction reaction by monitoring a physical characteristic of either the reducing agent or the reduction by-product. This method is, therefore, particularly applicable in the fabrication of an integrated circuit device, such as a CMOS transistor, an NMOS transistor, a PMOS transistor, or a bi-polar transistor.

Method of determining copper reduction endpoint in the fabrication of a semiconductor device

The present invention relates to an apparatus and method for depositing a film on a wafer. A reactor for depositing a film on a surface of a wafer comprises a processing chamber having an electrode, a ceramic wafer support supporting the wafer and separated from the electrode by a distance of between 230 and 240 millimeters, a gas inlet supplying gas reactants, and a radio frequency inlet supplying radio frequency energy. The reactor further comprises a heating chamber having at least one heat source which heats the wafer. A method for depositing a film on a surface of a semiconductor wafer comprises providing a processing chamber having a ceramic wafer support supporting the wafer and an electrode, separating the electrode from the ceramic wafer support by a distance of between 230 and 240 millimeters, supplying radio frequency energy into the processing chamber, supplying gas reactants into the processing chamber, and heating the wafer.

Method for enhanced dielectric film uniformity

A method of forming a passivation layer over features located on a top layer on a semiconductor device comprises depositing a first void-free layer of a dielectric over the top layer using high density plasma chemical vapor deposition. A second void-free layer can additionally be deposited over the first void-free layer. The first void-free layer can be formed from a silicon oxide, and the second void-free layer can be formed from a silicon nitride. The first void-free layer has a top surface that is disposed at a height higher than the features. The first void-free layer can be applied in two steps. First, the void-free layer is deposited at a D/S ratio between 3.0 and 4.0 to a depth of at least 40% of the feature's height, and then deposited at a D/S ratio of between 6.0 and 7.0.

High density plasma passivation layer and method of application

Integrated circuit fabrication includes the formation of tungsten contacts in windows. Between the tungsten and the contact region are Ti and TiN layers. Defects are prevented or reduced by sealing grain boundaries in the TiN layer prior to tungsten deposition. Grain boundaries are sealed by rinsing the TiN layer in water at ambient temperature or above.

Method of integrated circuit fabrication including a step of depositing

The use of a deposition process involving a plasma struck in a gas including tetraethoxysilane and a source of oxygen yields, at low temperatures, conformal coatings of silicon dioxide. This process has significant implications for semiconductor device fabrication involving the deposition of a dielectric over a metallic non-planar structure.

Low temperature deposition of silicon oxides for device fabrication

A method for forming a dielectric layer in an integrated circuit is disclosed. After a first dielectric layer is formed, a second dielectric layer is formed on top of the first layer. The second layer is formed by reducing precursor gas flow during the initial portion of the deposition process so that the initial film density of the deposited dielectric is higher or equal to the density of the bulk of the first and second dielectric.

Integrated circuit interlevel dielectric wherein the first and second

In plasma enhanced chemical vapor deposition (PECVD) of silicon dioxide on a substrate, voids and discontinuities are reduced by first depositing silicon dioxide in a sputter each chamber (22) in which a magnetic field is produced within the rf plasma for depositing the silicon dioxide. Simultaneous sputter etch and deposition occurs which inhibits net deposition at the corners of metal conductors over which the silicon dioxide is deposited. The substrate is then removed and transferred through a load lock (27) to a conventional PECVD deposition chamber (23).

Silicon dioxide deposition method using a magnetic field and both

In a radio-frequency plasma deposition reactor (10), SiO.sub.2 is deposited from a source (16) of tetraethoxysilane (TEOS). The deposition is made to be anisotropic, that is, to be deposited preferentially on horizontal surfaces, by use in the deposition atmosphere of a constituency such as NH.sub.3 or NF.sub.3 which inhibits SiO.sub.2 deposition, along with a radio-frequency power in excess of 100 watts, which preferentially removes the inhibiting gas from horizontal surfaces through ion impact.

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Orlando, FL, United States of America

Leonard Jay Olmer