Intel Corporation

Leonard J Schultz

William S Wu

Muthurajan Jayakumar

Kee Sup Kim

Dilip K Sampath

Bindi A Prasad

In a microprocessor system having a bus clock running at a bus clock rate, a method for reducing an idle interval between a first data transfer and a second data transfer, the method comprising the steps of:

Mechanism for data strobe pre-driving during master changeover on a

A scan chain for testing sequential logic circuitry includes a number of concatenated storage elements having a feedback loop from the output of the last storage element to the input of the first storage element. The storage elements are clocked by a chain clock signal at a frequency multiple of a base frequency. The number of storage elements in the scan chain is a relative prime with respect to the frequency multiple. Scan chains running at different frequency multiples of the base frequency may be concatenated with the output of the last storage element of one scan chain being coupled to the input of the first storage element of the next scan chain. Wherever the output of a storage element clocked on a leading phase of the chain clock signal is coupled to the input of a storage element clocked on a trailing phase of the chain clock signal, a buffer is inserted to buffer the output to the input.

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Hillsboro, OR, United States of America

Leonard J Schultz