U.S. Philips Corporation

Leonard J Esser

Leendert J Van De Polder

Arnoldus J Boudewijns

Jacobus G Bakker

Petrus J Van De Wiel

Ludovicus G Heldens

Eduard Ferdinand Stikvoort

Adrianus W Ludikhuize

Marcellinus J Pelgrom

Antonius G Verhulst

Marnix G Collet

Johannes A Van Haaren

Wilbert J Hartmann

Hermanus Josephus Wilting

Henricus M Vaes

Johannes A Van Gils

Matthias Johannes Theunissen

Leonardus A Daverveld

Gijsbert Lock

An LCD device in which the pixels are divided into sub-pixels composed of one analog adjustable sub-pixel and a plurality of digitally controlled other sub-pixels. By combining a discrete adjustment of the (sub)-transmission levels of the other sub-pixels with an analog adjustment of transmission levels of the one sub-pixel, the total number of light transmission levels is increased considerably. The analog adjustment thus is less critical because the greater part of the ultimate level is defined by the accurate discrete adjustment.

Electro-optic display device with increased number of transmission levels

In a CCD image sensor arrangement, during the transport through the CCD channels the distance between successive signal packets is enlarged and an empty potential well is induced between these packets, which is then transferred as a normal packet together with the signal charges. During the transport, in the said additional well charge is collected which is representative for the smear charge which is trapped during the transport by the corresponding signal packet. When during reading, the smear charge is subtracted from the signal charge, the accurate value of the smear-compensated signals can be determined.

CCD image sensor including smear suppression means

The invention relates to a charge-coupled device of the accordion type provided with a shift register for supplying accordion clock voltages on the one hand and with clock lines for supplying conventiional clock voltages on the other hand. The electrodes are alternatively coupled to the shift register and to the clock lines. The dissipation can be considerably reduced in this device. Moreover, the transport direction can be reversed in a simple manner, which is of importance, for example, in image sensors for smear suppression.

Accordion-type charge-coupled devices

A charge-coupled device comprising two clock electrodes (4,5) on the two opposite sides of the charge transport channel (3) and which extend the entire length of the channel. Charge storage regions (6-9) are located zigzagwise on both sides of the channel, as a result of which during charge transport the charge is transferred from one side to the other. Due to the separation of the electrodes the parasitic capacitance between them is low, achieving low power dissipation. The electrodes are located in grooves at the sides of the channel, leaving the surface of the channel unobstructed. The device can therefore serve as an image sensor of high sensitivity.

Charge-coupled device

The present invention involves a semiconductor device, such as a shift register, wherein information in the form of charge carriers is moved laterally through the bulk of a semiconductor layer by means of an electric field, while the charge carriers are stored at the surface of the semiconductor layer. According to this invention, information containing regions can be separated from each other by depletion zones extending through the thickness and the width of the semiconductor layer. Charge transport laterally through the interior of the semiconductor layer results in a considerable reduction of the transport time. Majority charge carriers are advantageously used.

Semiconductor device

The invention relates to a charge-coupled image sensor of the line transfer type comprising a number of parallel lines (2-6) which are each constituted by an n-phase CCD. An electrode (12-16) of each CCD is arranged parallel to this CCD separately for each CCD. The other (n-1) electrodes (17-20) extend transversely to the charge transport direction over all CCD's. The first-mentioned electrode (12-16) is used as a selection gate and is moreover used, depending upon the applied voltage, as an integration gate or as a blocking gate during the integration period.

Charge coupled sensor arrangement

A color television Y/U/V luminance-chrominance multiplex signal with signals which may or may not be compressed in time comprises for a television line the associated luminance information Y and half the chrominance information U or V. As a result the circuit should supply the chrominance information directly (U, V) and repeatedly (U', V') during a subsequent television line. To avoid the use of an accurate, expensive delay device having a line period delay, the circuit includes an input shift register (A) of the series-in, parallel-out type, which is coupled through an on-off switch circuit (B1, B2) to parallel inputs of two shift registers (C1, C2) of the parallel-in, series-out type. During a line blanking period (THB) writing is effected from the input shift register in the output shift registers and during two subsequent line scan periods (THS1, THS2) reading is effected consecutively therefrom. Reading may be effected in opposite phase if a repetition is to be effected after exactly one line period.

Circuit for converting a colour television time division multiplex

A semiconductor device including a field effect transistor, such as an insulated gate field effect transistor, which has in the direction from source zone to drain zone successive first and second channel zones with associated gate electrode parts. According to the invention, over at least 80% of the overall channel width, in a direction at right angles to the direction of source-drain current, the ratio L.sub.1 /L.sub.2 between the length L.sub.1 of the first gate electrode part and the length L.sub.2 of the second gate electrode part is variable and smaller than unity in order to improve the linearity of the field effect transistor.

Semiconductor device having a field effect transistor with improved

A semiconductor device comprising a field effect transistor of the lateral or vertical DMOST type having a source zone of the one conductivity type, an adjoining channel region of the other conductivity type, a drain zone of the one conductivity type and a weakly doped drift region located between the drain zone and the channel region. According to the invention a second gate electrode located on the side of the drain zone and separated from the first gate electrode is disposed on the insulating layer above the channel zone behind the first gate electrode located on the side of the source zone. The length L.sub.2 of the part of the second gate electrode located above the channel zone is at least equal to that of the part of the first gate electrode located above the channel zone. As a result, a high value of the mutual conductance g.sub.m as well as good linearity can be obtained. The second gate electrode is preferably made of polycrystalline silicon,which in the operating condition is depleted at least in part above the drift region.

Insulated dual gate field effect transistor

In a CCD, especially in an image sensor device, the information density can be doubled by sequentially switching the electrodes between a clock signal and a reference signal. Clock signals and reference signals are obtained as output signals of a shift register controlled by a monophase or multiphase clock. The register is provided, for example, using C-MOS technology. Information at the input terminal of the first stage of the shift register in combination with clock pulse signals at the register clock, determine the output signals of the next stage of the shift register. Hence, these input signals determine the voltage variations at the electrodes connected to the outputs of the register stages.

Charge coupled semiconductor device with dynamic control

In a charge transfer device in accordance with the invention, the channel is subdivided at the area of the output into two subchannels provided with separate output gates which are clocked in phase opposition, and with separate reset gates which are likewise clocked in phase opposition. Between the output gates and the reset gates there is arranged a floating gate common to both subchannels by which signals can be read during 100% of a clock period so that no additional filtering operations for filtering out spectra of higher order are required. This output circuit can be used in applications in which high speeds and a high sensitivity are required.

Charge transfer device having a subdivided channel output region

By the use of high-ohmic polycrystalline silicon (poly) in MIS elements, a depletion layer can be formed in the poly material which brings about an electric decoupling between the poly (gate) and the underlying semiconductor body. This effect can be utilized advantageously in various circuit elements, such as in CCD's, in order to obtain a favorable potential distribution in the substrate; in MOS transistors in order to reduce the parasitic capacities; and in high-voltage devices in order to increase the breakdown voltage at the edge of the field plate (resurf).

Charge-coupled buried-channel device with high-resistivity gate

By the use of high-ohmic polycrystalline silicon(poly) in MIS elements, a depletion layer can be formed in the poly material which brings about an electric decoupling between the poly (gate) and the underlying semiconductor body. This effect can be utilized advantageously in various circuit elements, such as in CCD's, in order to obtain a favorable potential distribution in the substrate; in MOS transistors in order to reduce the parasitic capacities; and in high-voltage devices in order to increase the breakdown voltage at the edge of the field plate (resurf).

MIS high-voltage element with high-resistivity gate and field-plate

By the use of high-resistivity polycrystalline silicon (poly) in MIS elements, a depletion layer can be formed in the poly material which brings about an electric decoupling between the poly (gate) and the underlying semiconductor body. This effect can be utilized advantageously in various circuit elements, such as in CCD's, in order to obtain a favorable potential distribution in the substrate; in MOS transistors in order to reduce the parasitic capacities; and in high-voltage devices in order to increase the breakdown voltage at the edge of the field plate (resurf).

DMOS with high-resistivity gate electrode

A television pick-up arrangement comprising a solid-state picture pick-up device rows of picture pick-up elements of which are connectable to parallel inputs of two output shift registers. When the shift registers are read simultaneously they supply at their series outputs picture signal which are associated with each time two pairs of rows of picture pick-up elements. According to the invention, the two picture signals are applied on the one hand separately to a vertical aperture correction circuit having only one delay device with a time delay of one line period and on the other hand combined to a horizontal aperture correction circuit, the corrected signals being combined behind said correction circuits. Advantageous use can then be made of a device in which pick-up information is obtained by both holes and electrons which are caused by photons.

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Eindhoven, Netherlands

Leonard J Esser