Micron Technology Incorporated

Sionyx, Inc.

Other

Micro Technology, Inc.

Mosaid Technologies Corporation

Round Rock Research, LLC

Intellectual Ventures Ii LLC

Hewlett-packard Company

Empire Technology Development LLC

Mircon Technology, Inc.

Micron Corporation

Micron Technoloy, Inc

Micron Tecnology, Inc.

Ladarsystems, Inc.

Leonard Forbes

Kie Y Ahn

Wendell P Noble

Joseph E Geusic

Arup Bhattacharyya

Paul A Farrar

Jerome Michael Eldridge

Salman Akram

Alan R Reinberg

Eugene H Cloud

Homayoon Haddad

David R Cuthbert

Drake Miller

Jutao Jiang

Jeffrey McKee

Chintamani Palsule

Badih El-Kareh

Kirk D Prall

Luan C Tran

Jaroslav Hynecek

Hussein Ibrahim Hanafi

Thomas Joy

Brent Keeth

David J McElroy

Warren M Farnworth

Chen Feng

Kevin G Donohoe

Wayne P Richling

Ki Y Ahn

Kiey Y Ahn

Vinit Dhulla

David J Mcelroy

Photosensitive devices and associated methods are provided. In one aspect, for example, a photosensitive imager device can include a semiconductor substrate having multiple doped regions forming at least one junction, a textured region coupled to the semiconductor substrate and positioned to interact with electromagnetic radiation, and an electrical transfer element coupled to the semiconductor substrate and operable to transfer an electrical signal from the at least one junction. In one aspect, the textured region is operable to facilitate generation of an electrical signal from the detection of infrared electromagnetic radiation. In another aspect, interacting with electromagnetic radiation further includes increasing the semiconductor substrate's effective absorption wavelength as compared to a semiconductor substrate lacking a textured region.

Photosensitive imaging devices and associated methods

Backside illuminated photosensitive devices and associated methods are provided. In one aspect, for example, a backside-illuminated photosensitive imager device can include a semiconductor substrate having multiple doped regions forming a least one junction, a textured region coupled to the semiconductor substrate and positioned to interact with electromagnetic radiation where the textured region includes surface features sized and positioned to facilitate tuning to a preselected wavelength of light, and a dielectric region positioned between the textured region and the at least one junction. The dielectric region is positioned to isolate the at least one junction from the textured region, and the semiconductor substrate and the textured region are positioned such that incoming electromagnetic radiation passes through the semiconductor substrate before contacting the textured region. Additionally, the device includes an electrical transfer element coupled to the semiconductor substrate to transfer an electrical signal from the at least one junction.

Process module for increasing the response of backside illuminated photosensitive imagers and associated methods

Backside illuminated photosensitive devices and associated methods are provided. In one aspect, for example, a backside-illuminated photosensitive imager device can include a semiconductor substrate having multiple doped regions forming a least one junction, a textured region coupled to the semiconductor substrate and positioned to interact with electromagnetic radiation, and a passivation region positioned between the textured region and the at least one junction. The passivation region is positioned to isolate the at least one junction from the textured region, and the semiconductor substrate and the textured region are positioned such that incoming electromagnetic radiation passes through the semiconductor substrate before contacting the textured region. Additionally, the device includes an electrical transfer element coupled to the semiconductor substrate to transfer an electrical signal from the at least one junction.

A first conductive region having a second conductivity type is formed in a first semiconductor over a first dielectric isolation region and having a first conductivity type. A second semiconductor having the first conductivity type is formed over the first conductive region and the first semiconductor. Isolation structures are formed extending through the second semiconductor and the first semiconductor to the first dielectric isolation region, thereby defining a first well of the second semiconductor contained within the isolation structures and a second well of the first conductive region contained within the isolation structures. A charge-storage node is formed over the first well. Source/drain regions having the second conductivity type are formed in the first well adjacent the charge-storage node. A control gate is formed over the charge-storage node. A first contact is formed to the first well. A second contact is formed to the second well through the first well.

Methods of forming memory devices with isolation structures

An avalanche photodiode device operated in Geiger-mode, the device comprising a P-N junction formed on a substrate with a first semiconductor region and a second semiconductor region with an anode and cathode. The device further comprising a third semiconductor region, the third semiconductor region in physical contact with the second region, not in physical contact with the first region, and being the same semiconductor-type as the first semiconductor region. Additionally comprising a diode on the second semiconductor region and having a turn-on voltage than the P-N junction.

Clamped avalanche photodiode

A backside illuminated image sensor includes a substrate, a backside passivation layer disposed on backside of the substrate, and a transparent conductive layer disposed on the backside passivation layer.

Backside illuminated image sensor

Stacked imager devices that can determine distance and generate three dimensional representations of a subject and associated methods are provided. In one aspect, an imaging system can include a first imager array having a first light incident surface and a second imager array having a second light incident surface. The second imager array can be coupled to the first imager array at a surface that is opposite the first light incident surface, with the second light incident surface being oriented toward the first imager array and at least substantially uniformly spaced. The system can also include a system lens positioned to direct incident light along an optical pathway onto the first light incident surface. The first imager array is operable to detect a first portion of the light passing along the optical pathway and to pass through a second portion of the light, where the second imager array is operable to detect at least a part of the second portion of light.

Three dimensional imaging utilizing stacked imager devices and associated methods

Various embodiments includes a stacked open pattern inductor fabricated above a semiconductor substrate. The stacked open pattern inductor includes a plurality of parallel open conducting patterns embedded in a magnetic oxide or in an insulator and a magnetic material. A layer of magnetic material may be located above the inductor and below the inductor to confine electronic noise generated in the stacked open pattern inductor to the area occupied by the inductor. The stacked open pattern inductor may include a magnetic material directly contacts one of the conducting patterns and the substrate. The stacked open pattern inductor may be fabricated using conventional integrated circuit manufacturing processes, and the inductor may be used in connection with computer systems.

Process of manufacturing an open pattern inductor

One aspect of the present subject matter relates to a memory. A memory embodiment includes a nanofin transistor having a first source/drain region, a second source/drain region above the first source/drain region, and a vertically-oriented channel region between the first and second source/drain regions. The nanofin transistor also has a surrounding gate insulator around the nanofin structure and a surrounding gate surrounding the channel region and separated from the nanofin channel by the surrounding gate insulator. The memory includes a data-bit line connected to the first source/drain region, at least one word line connected to the surrounding gate of the nanofin transistor, and a stacked capacitor above the nanofin transistor and connected between the second source/drain region and a reference potential. Other aspects are provided herein.

DRAM with nanofin transistors

Electronic apparatus and methods of forming the electronic apparatus include a gallium lanthanide oxide film for use in a variety of electronic systems. The gallium lanthanide oxide film may be structured as one or more monolayers. The gallium lanthanide oxide film may be formed using atomic layer deposition.

Gallium lanthanide oxide films

Growing community of inventors

Corvallis, OR, United States of America

Leonard Forbes