Intel Corporation

Leonard C Pipes

Bernhard Sell

Mark Y Liu

Chieh-Jen Ku

Pei-Hua Wang

Mitchell C Taylor

Rita Slilaty

Rishabh Mehandru

Stephen M Cea

Aaron D Lilak

Cory E Weber

Patrick H Keys

Martin M Mitan

Dennis G Hanken

Sang-Won Park

Harish Ganapathy

Tzu-Min Ou

Jack Yaung

Seahee Hwangbo

Sishir Bhowmick

Fin doping, and integrated circuit structures resulting therefrom, are described. In an example, an integrated circuit structure includes a semiconductor fin. A lower portion of the semiconductor fin includes a region having both N-type dopants and P-type dopants with a net excess of the P-type dopants of at least 2E18 atoms/cm. A gate stack is over and conformal with an upper portion of the semiconductor fin. A first source or drain region is at a first side of the gate stack, and a second source or drain region is at a second side of the gate stack opposite the first side of the gate stack.

Fin doping and integrated circuit structures resulting therefrom

Embodiments herein describe techniques for a transistor above a substrate. The transistor includes a channel layer above the substrate. The channel layer includes a first channel material of a first conductivity. In addition, the channel layer further includes elements of one or more additional materials distributed within the channel layer. The channel layer including the elements of the one or more additional materials has a second conductivity different from the first conductivity. Other embodiments may be described and/or claimed.

Channel formation for three dimensional transistors

Embodiments disclosed herein include transistors and methods of forming such transistors. In an embodiment, the transistor may comprise a semiconductor channel with a first surface and a second surface opposite the first surface. In an embodiment, a source electrode may contact the first surface of the semiconductor channel and a drain electrode may contact the first surface of the semiconductor channel. In an embodiment, a gate dielectric may be over the second surface of the semiconductor channel and a gate electrode may be separated from the semiconductor channel by the gate dielectric. In an embodiment, an isolation trench may be adjacent to the semiconductor channel. In an embodiment, the isolation trench comprises a spacer lining the surface of the isolation trench, and an isolation fill material.

Isolation gap filling process for embedded dram using spacer material

Disclosed herein are techniques for providing isolation in integrated circuit (IC) devices, as well as IC devices and computing systems that utilize such techniques. In some embodiments, a protective layer may be disposed on a structure in an IC device, prior to deposition of additional dielectric material, and the resulting assembly may be treated to form a dielectric layer around the structure.

Isolation in integrated circuit devices

Ions are implanted into the dielectric layer and/or barrier layer over a semiconductor substrate to change the polish rates of either or both layers during formation of a shallow trench isolation (STI) structure. The ion implantation can change or affect the polish rates of the material and the polish selectivity, and reduce or minimize unwanted topography resulting from chemical mechanical polishing (CMP). After CMP, the resulting STI structure has a more uniform and smooth topography.

Shallow trench isolation structures having uniform and smooth topography

Implanting ions in shallow trench isolation structures

A shallow trench isolation (STI) structure is formed by etching trenches into the surface of a substrate in alignment with a patterned masking layer. An ion implantation of, for example, carbon, nitrogen, or oxygen, is performed so as to create an electrically insulating layer extending downwardly from a bottom surface of the trench. By implanting such extensions, STI structures with greater effective aspect ratios may be obtained which, in turn, allow greater packing density in integrated circuits. Implanted isolation structures may be formed without etching a trench by implanting into regions of the substrate. In this way, trench etch, dielectric back-fill, and planarization operations can be eliminated. Furthermore the implanted regions may be formed by multiple implants at different energies so as to obtain multiple, typically contiguous, target ranges. Ions of various masses or charges may be used so as to obtain the desired implant depth and concentration profile in the isolation structures, independent of whether these structures are trench extensions or formed directly beneath a planarized substrate surface.

Extension of shallow trench isolation by ion implantation

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Beaverton, OR, United States of America

Leonard C Pipes