Micron Technology Incorporated

Intel Corporation

Leon Zlotnik

Leonid Minz

Ekram H Bhuiyan

Brian Toronyi

Yoav Weinberg

Eyal En Gad

Jeremy R Anderson

Lev Zlotnik

Pranjal Chauhan

Fan Zhou

Sureshkumar Shastry Vemuri

Daniel Ballegeer

An apparatus includes a memory resource configured to store data entries in a data memory resource including a first data structure and a second data structure and a processing device coupled to the memory resource. The processing device is configured to determine a predicted address location in the first data structure, compare the predicted address location to at least one address threshold, alter the predicted address location to an altered predicted address location, determine an equivalent address location in a second data structure that is equivalent to the altered predicted address location, and write the data entry to the equivalent address location in the second data structure.

Predictive center allocation data structure

A plurality of data entries are written in a first memory bank that comprises a portion of a data structure that is stored across a plurality of memory banks. For a subsequent data entry, a determination is made that the subsequent data entry has a value that is greater than a first data entry among the plurality of data entries in the first memory bank and less than a second data entry among the plurality of data entries in the first memory bank. The subsequent data entry is written to an address location in a second memory bank of the plurality of memory banks that is between a lowermost address location and an uppermost address location of the second memory bank and a first bit corresponding to the address location in the second memory bank to which the subsequent data entry was written is stored in the data structure.

Scheme for data entry insertion in a sparsely populated data structure

A method includes receiving, by shift circuitry, a bit string comprising a plurality of bits and determining, based on a shifting indicator, a quantity of bits by which the bit string is to be shifted within the shift circuitry. The method further includes generating a shifted bit string by performing, by the shift circuitry, an operation to shift the bit string by the quantity of bits indicated by the shifting indicator and performing, by decision circuitry coupled to the shift circuitry, an operation to alter one or more of the plurality of bits of the shifted bit string from a logical value of one to a logical value of zero or from a logical value of zero to a logical value of one.

Syndrome decoding system

A method includes receiving signaling indicative of a temperature of a circuit portion area of a memory sub-system and receiving signaling indicative of a voltage or a current of the circuit portion area of the memory sub-system. The method further includes generating, based on the signaling indicative of temperature of the circuit portion area and the signaling indicative of the voltage or the current of the circuit portion area, a voltage management control signal and transferring the voltage management control signal to a voltage regulator of the memory sub-system. The method further includes operating the voltage regulator in response to receipt of the voltage management control signal to generate a voltage signal.

Temperature-based voltage management

Clock enable signals are collected and summed. The number of simultaneously enabled clock enable signals can represent switching activity within a system and can be used as an indicator for power management, noise management, etc. of such a system. Digital switching activity sensing include performance of an operation to sum a quantity of open clock gates associated with a plurality of latches that are grouped into multiple subsets of latches. An activity indication is generated based, at least in part, on a result of the operation to sum the quantity of open clock gates associated with the plurality of latches.

Digital switching activity sensing

A first data entry is written to an address location of a memory resource that is neither a first physical address nor a last physical address. In response to a determination that a second data entry has a value that is greater than a value associated with the first data entry, the second data entry is written to an address location that is physically located between the address location of the memory resource to which the first data entry is written and the last physical address. In response to a determination that the second data entry has the value that is less than the value associated with the first data entry, the second data entry is written to an address location that is physically located between the address location of the memory resource to which the first data entry is written and the first physical address.

Center allocation data structure

A decoding operation is performed by altering at least one bit of the bit string from a first value to a second value and applying a bit mask to each bit of the bit string that is not altered from the first value to the second value. The decoding operation further includes writing an indication corresponding to a quantity of bits that have been altered from the first value to the second value to an array of memory cells, wherein the indication corresponds to a quantity of errors contained in the bit string, determining that the quantity of errors for the bit string has reached a threshold quantity of errors, and refraining from performing a subsequent operation to alter at least the one bit of the bit string, or a different bit of the bit string, or both, from the first value to the second value in response to determining that the quantity of errors for the bit string has reached the threshold quantity of errors.

Bit mask for syndrome decoding operations

A hash corresponding to a bit string is generated. The hash corresponds to an address location in a data structure associated with the bit string. An index and a modifier correspond to the address location in the data structure corresponding to the hash associated with a first address location in the data structure are determined. In response to determining that the modifier has a first value associated therewith, index information corresponding to the bit string is written to the first address location in the data structure. In response to determining that the modifier has a second value other than the first value associated therewith, the index information corresponding to the bit string is written to a second address location in the data structure.

Database management

An example method for scan-based voltage frequency scaling can include performing a plurality of at-speed scan operation on a system on chip (SoC) at a plurality of respective voltage values. The example method can include entering data gathered from at least one of the plurality of at-speed scan operations into a database. The entered data is associated with the respective plurality of voltage value. The example method can include determining a particular voltage value of the respective plurality of voltage values at which a parameter of the SoC reaches a threshold. The example method can include indicating the determined particular voltage in the database. The indicated determined particular voltage in the database can be used for performing one or more operations using the SoC.

Scan-based voltage frequency scaling

An example method for voltage frequency scaling based on error rate can include performing a plurality of monitoring operations on a system on chip (SoC) at a respective plurality of voltage values (and/or plurality of frequency values and/or temperature values). The example method can include causing error rate data gathered from each of the plurality of monitoring operations to be entered into a database, wherein the entered error rate data is associated with the plurality of voltage values. The entered data is associated with the respective plurality of voltage value. The example method can include generating a plot using the error rate date in the database. The example method can include determining a particular voltage value greater than each of the plurality of voltage values based on the plot and a particular error rate associated with the particular voltage value.

Voltage frequency scaling based on error rate

A method includes determining a quantity of errors for a bit string based on a quantity of bits having a logical value of one within the bit string and writing an indication corresponding to the quantity of errors for the bit string to an array of memory cells. The method can further include determining that the quantity of errors for the bit string has reached a threshold quantity of errors and refraining from performing a subsequent operation to determine the quantity of errors for the bit string in response to determining that the quantity of errors for the bit string has reached the threshold quantity of errors.

A plurality of flip-flops of an integrated circuit (IC) (e.g., an ASIC) are electrically connected in a predefined series. The scan input gate of any give flip-flop in the predefined series is electrically connected to one of a Q output gate or a Q-bar output gate of an adjacent flip-flop in the predefined series. A reset operation for the IC occurs by feeding a bit string of identical bits (e.g., all zeros) through the scan input gate of a first flip-flop of the plurality of flip-flops to reset the plurality of flip-flops without the need for resetting circuitry and accompanying power savings for the IC.

Resetting integrated circuits

A first memory resource is configured to store a data structure. The first memory resource is coupled to a second memory resource that is configured to store a plurality of data structures. A processing device is coupled to the first memory resource, the second memory resource, and a third memory resource. The processing device writes data entries to the data structure within the first memory resource, determine that the data structure within the first memory resource includes a threshold quantity of data entries, and write the contents of the data structure within the first memory resource to a data structure within the second memory resource. The processing resource is further configured to move the contents of the contents of the data structure in the second memory resource to the third memory resource by readdressing the entries written within the second memory resource to virtual addresses associated with the third memory resource.

Virtual binning in a memory device

A voltage tracking circuit includes delay line blocks, a phase detector delay line block, phase detection circuitry, and a controller. The controller determines a first voltage based on a quantity of active delay line blocks among the plurality of delay line blocks and determines a second voltage based on information received from the phase detection circuitry. The controller determines a measured value of a voltage provided by the voltage regulator voltage based on the first voltage and the second voltage.

Voltage tracking circuit

An asynchronous multi-cycle reset synchronization circuit that can correlate any number of resets and synchronous clocks with simultaneous reset de-assertion and removal of reset assertion crossing hazards. The asynchronous multi-cycle reset synchronization circuit can also be paired with a synchronous multi-cycle reset synchronization circuit to correlate same domain asynchronous and synchronous resets. Also described is a synchronous reset multi-cycle synchronization circuit that correlates with any number of asynchronous resets and guarantees simultaneous reset de-assertion.

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Camino, CA, United States of America

Leon Zlotnik