International Business Machines Corporation

Other

Leon Skarshinski

Thomas Anthony Gregg

Karl H Hoppe

Frank David Ferraiolo

Peter Anthony Franaszek

Steven Frederick Oakland

Ilya I Novof

Joseph C Elliott

Roland A Bechade

Martin W Sachs

Paul J Brown

Kenneth R Lynch

Kenneth J Shaw

Salvatore A Calta

Richard Strangwayes

Bruce Kaufmann

Laura H McGoogan

Michael E Underkoffler

A computer interconnection system provides dynamic switch cascading with a plurality of circuit switches having circuit switch ports coupled by a dynamic connection to provide a dynamically cascadable switching network having a plurality of nodes, including end point and switch nodes. Two individual circuit switches of the network are interconnected by a cross-link group of one or more links. The system transmits frame information including a source endpoint address and a destination endpoint address, each of which can be associated with an endpoint port or a cross-link group, and forms a connection between an endpoint port or a cross-link group to make a connection between a circuit switch port corresponding to a source endpoint address and a circuit switch port corresponding to the destination endpoint. The dynamic circuit switch connections, as applicable to dynamic switch cascade operation, is compatible with the ESCON I/O Interface Architecture or to a fabric node supporting the Class 1 service defined by the Fibre Channel ANSI Standard.

Dynamic switch cascading system

A process independent digital clock signal timing network is described for generating a chip clock substantially in phase with and offset by one cycle from an input clock signal. The timing network determines the delay experienced by a clock signal passing through a predetermined internal clock circuit on the chip and pregates the internal clock circuit by an amount equivalent to the determined delay such that the chip clock signal output from the internal clock circuitry lags the external clock signal input to the semiconductor chip by one cycle. Various timing network embodiments are described and claimed.

Clock signal latency elimination network

A dynamic switch and its protocol for establishing dynamic connections in a link by the use of frames, each frame having an identification of the source of the frame, an identification of the destination of the frame for the requested connection, and link controls to maintain, initiate or terminate a connection between the source and the destination. The frames are bounded by a start of frame delimiter and an end of frame delimiter which may also act as a connect link control and a disconnect link control, respectively, and the connections are made through the dynamic switch having dynamic-switch ports. The state of a dynamic-switch port is changed dependent on its present state, the dynamic connection requested, and the direction and type of frames passing through the dynamic-switch port.

Switch and its protocol for making dynamic connections

An apparatus and method for transmitting commands over a serial link having a switch intermediate a channel and a control unit wherein continuous sequences of idle characters (K.28.5) are sent over the link for maintaining character synchronization. Commands and response information is sent between ports of the switch and the channel and/or the control unit by modifying every other idle character to a modified idle character to which a command or response function has been assigned. In the modification, a selected number of the bits of the idle character are held invariant, and only those bits are varied which form data characters according to the rules of the 8B/10B encoding method. Code points for a total of 124 modified idle characters are disclosed to which a separate command or response may be assigned.

Transmitting commands over a serial link

A channel subsystem with a conventional serial extender link that causes communications between a channel and a control unit to be delayed by the additional time to transmit a message in one direction and to transmit an acknowledgement in the other direction. The channel subsystem also has a buffer and associated components (called a channel outboard box) that are used for prefetching data from processor memory or from a peripheral device without waiting for the acknowledgment routines that are commonly used on both an interlocked data transfer and a non-interlocked transfer (called data streaming). A system of counters and other components and associated operations maintain the correct byte count that would otherwise be maintained in a system without the prefetch buffer and with only a short serial link. A system of count and status frames provides for sending byte count and other status information between the channel and the outboard box.

Byte count handling in serial channel extender with buffering for data

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Leon Skarshinski