International Business Machines Corporation

Other

Columbia University

Consolidated Edison Company of New York, Inc.

Akw Analytics Inc.

Leon L Wu

Roger N Anderson

Arthur Kressner

Herbert I Stoller

Richard R Konian

John M Angiulli

Charles J Kraus

Boyi Xie

Albert Boulanger

Irving Feinberg

Eugene S Kolankowsky

Moises Cases

David Meltzer

Terence K Rodrigues

Wen-Yuan Wang

Warren D Grobman

Samuel R Levine

Edmund Sutherland Gamble

Maggie Chow

Arun K Ghose

David Waltz

Leo Yuan

Rebecca J Passonneau

Cynthia Rudin

Axinia Radeva

Peter Hofmann

Frank Dougherty

Ansaf Salleb-Aouissi

Serena Lee

Haimonti Dutta

By Paula Kraus, Executrix

Phil Gross

Charles J Kraus, Deceased

Huang Bert

Steve Ierome

Delfina Isaac

Electric Grid Analytics Learning Machine, EGALM, is a machine learning based, 'brutally empirical' analysis system for use in all energy operations. EGALM is applicable to all aspects of the electricity operations from power plants to homes and businesses. EGALM is a data-centric, computational learning and predictive analysis system that uses open source algorithms and unique techniques applicable to all electricity operations in the United States and other foreign countries.

Electric grid analytics learning machine

Energy Analytics Learning Machine (or EALM) system is a machine learning based, 'brutally empirical' analysis system for use in optimizing the payout from one or more energy sources. EALM system optimizes exploration, production, distribution and/or consumption of an energy source while minimizing costs to the producer, transporter, refiner and/or consumer. Normalized data are processed to determine clusters of correlation in multi-dimensional space to identify a machine learned ranking of importance weights for each attribute. Predictive and prescriptive optimization on the normalized energy data is performed utilizing unique combinations of machine learning and statistical algorithm ensembles. The unstructured textual energy data are classified to correlate with optimal production to capture the dynamics of one or more energy sources of physically real or theoretically calculated systems to provide categorization results from labeled data sets to identify patterns.

Energy analytics learning machine

Petroleum Analytics Learning Machine (or PALM) system is a machine learning based, 'brutally empirical' analysis system for use in all upstream and midstream oil and gas operations. PALM system optimizes exploration, production and gathering from at least one well of oil and natural gas fields to maximize production while minimizing costs. Normalized data are processed to determine clusters of correlation in multi-dimensional space to identify a machine learned ranking of importance weights for each attribute. Predictive and prescriptive optimization on the normalized data is performed utilizing unique combinations of machine learning and statistical algorithm ensembles. The unstructured textual data are classified to correlate with optimal production to capture the dynamics of at least one or more wells of oil and natural gas fields and to provide categorization results from labeled data sets to identify patterns.

Petroleum analytics learning machine system with machine learning analytics applications for upstream and midstream oil and gas industry

A machine learning system for ranking a collection of filtered propensity to failure metrics of like components within an electrical grid that includes a raw data assembly to provide raw data representative of the like components within the electrical grid; (b) a data processor, operatively coupled to the raw data assembly, to convert the raw data to more uniform data via one or more data processing techniques; (c) a database, operatively coupled to the data processor, to store the more uniform data; (d) a machine learning engine, operatively coupled to the database, to provide a collection of propensity to failure metrics for the like components; (e) an evaluation engine, operatively coupled to the machine learning engine, to detect and remove non-complying metrics from the collection of propensity to failure metrics and to provide the collection of filtered propensity to failure metrics; and (f) a decision support application, operatively coupled to the evaluation engine, configured to display a ranking of the collection of filtered propensity to failure metrics of like components within the electrical grid.

Machine learning for power grid

Techniques for evaluating the accuracy of a predicted effectiveness of an improvement to an infrastructure include collecting data, representative of at least one pre-defined metric, from the infrastructure during first and second time periods corresponding to before and after a change has been implemented, respectively. A machine learning system can receive compiled data representative of the first time period and generate corresponding machine learning data. A machine learning results evaluator can empirically analyze the generated machine learning data. An implementer can implement the change to the infrastructure based at least in part on the data from a machine learning data outputer. A system performance improvement evaluator can compare the compiled data representative of the first time period to that of the second time period to determine a difference, if any, and compare the difference, if any, to a prediction based on the generated machine learning data.

Metrics monitoring and financial validation system (M2FVS) for tracking performance of capital, operations, and maintenance investments to an infrastructure

Aspects for improving signal quality on high speed, multi-drop busses are described. The aspects include coupling a source device directly to multiple load devices, wherein there are no resistance components coupled in series between the source device and the multiple load devices. The aspects further include providing a spacing arrangement for the multiple load devices, wherein negative reflections are delayed to minimize deleterious efforts from the negative reflections. Through the present invention, the modified version of a commonly used bus topology achieves extended voltage timing margins in a high speed, multi-drop bus in a straightforward and efficient manner.

Method and topology for improving signal quality on high speed, multi-drop busses

A data processing system includes first, second, and third agents connected to a shared bus. The third agent is able to receive information via the shared bus from the first agent or from the second agent. The third agent includes a skew compensation circuit to determine signal skew in signal received via the shared bus and to compensate for the skew by adding delay into selected signals of the bus. The skew compensation circuit determines whether the first agent or the second agent is the sender of information received by the third agent via the shared bus. The skew compensation circuit alters the skew compensation based on the identity of the sender such that the delay into the bus signals is specific to the corresponding sender.

Skew compensation for a multi-agent shared bus

A preferred embodiment includes a distributed network of a plurality of dynamically configurable bi-directional input/output (I/O) cells, each including a forward datapath having a first receiver, for receiving a first input signal from downstream driver on a first port of a signal line, coupled to a first driver for sending a first output signal to a first upstream receiver on a second port of the signal line; and a reverse datapath having a second receiver, for receiving a second input signal from a second downstream driver on the second port of the signal line, coupled to a second driver for sending a second output signal to a second upstream receiver on the first port of the signal line; wherein the first input signal and the second output signal are transmitted concurrently on the first port of the signal line.

Method and system for intelligent bi-direction signal net with dynamically configurable input/output cell

A memory system for a data processor whereby a plurality of memory devices, or storage chips, are coupled to a memory controller. There may be one, two, or more such memory devices, wherein some of the memory devices may be coupled to the memory controller via a single data bus, with an alternative embodiment including a second plurality of such memory devices coupled to the memory controller via a second data bus. Two separate clock buses are used to transport data between the memory controller and the various memory devices. A first clock bus is used to synchronize the transfer of data from the memory controller to a memory device. This clock bus will have a clock signal generated at the memory controller through a clock generation circuitry as a function of a system clock received by the memory controller. A similar clock generation circuitry at the memory device will receive the clock signal in order to synchronize the transfer of the data from a sending latch of the memory controller to a receiving latch in the memory device. A separate clock bus is used to transfer data from a memory device to the memory controller. Again, a clock signal is generated at the memory controller and sent on the second clock bus to the memory device. Clock generation circuits at the memory controller and at the memory device synchronize the sending latch at the memory device with the receiving latch at the memory controller. Both of the clock signals are synchronized with each other and with the received system clock.

Synchronized signal transfer system

A synchronizer for providing a source-synchronized clock bus reduces the effect of clock skew during the signal capturing process. The synchronizer includes at least one capture latch in the capture clock domain for capturing the signal, at least one storage latch for storing the signal coupled to the at least one capture latch, and a multiplexer coupled to the at least one storage latch. The multiplexer synchronizes data transfer of the at least one storage latch and the at least one capture latch, and an internal latch in the internal clock domain. The signal is controlled and processed by strobe signals and clock signals from the sending chip.

Synchronizer for a source synchronized clock bus with multiple agents

A method for manufacturing package structure integrated circuit chips having a heat spreader is disclosed. A wiring substrate is first provided. An integrated circuit chip, having a first surface and a second surface, is then electrically and mechanically connected to the wiring substrate via a first set of solder joints. A heat spreader is subsequently connected to the second surface of the integrated circuit chip via a second set of solder joints. The heat spreader includes an adhesion-promotion layer on a silicon layer.

Method for manufacturing a package structure having a heat spreader for

Memory chips (15) are mounted perpendicularly on a memory module substrate (14) to achieve a close spacing between the chips. A plurality of memory chip signal lines (20) are located on the memory module substrate (14) and the memory chips (15) are electrically coupled to the memory chip signal lines at spaced apart chip coupling points (23). Digital signals are driven to the memory chip signal lines (20) through signal lines (21) having a first level impedance. The memory chip signal lines (20) have a second level impedance greater that the first level impedance. The spacing between the chip coupling points (23) is chosen such that the effective impedance level of the memory chip signal lines (20) substantially matches the lower, first level impedance.

High frequency memory module

In order to transmit several data words in succession over a bus between components in a data processing system, the skew between the various bus lines has to be compensated in order that each data word is accurately received. The skew compensation is implemented by setting predetermined delays on certain bus lines in response to the comparison of a test pattern with an ideal situation.

System and method for alleviating skew in a bus

A decoupling capacitor for an integrated circuit is operatively coupled to a supply and to control circuitry for isolating the capacitor. The control circuitry automatically isolates the capacitor in response to a current through the capacitor exceeding a certain threshold, but tends to restore the capacitor to operation if the current is merely caused by momentary conditions, rather than substantial failure of the capacitor. The control circuitry includes a first control device for automatically switching to an off state to isolate the capacitor in response to a voltage produced by the current exceeding a certain threshold. A discharging device tends to discharge the voltage and automatically turn on the first device when the current is caused by momentary conditions. The discharging device may include a control device responsive to an external control signal for switching the first control device on and off.

Method and apparatus for reducing disturbances on an integrated circuit

An improved package structure for integrated-circuit chips is disclosed. In accordance with a preferred embodiment of the present invention, the integrated-circuit packaged structure comprises a wiring substrate, an integrated-circuit chip, and a heat spreader. The integrated-circuit chip has a first surface and a second surface, wherein the first surface is electrically and mechanically connected to the wiring substrate via a first set of solder joints. The heat spreader is connected to the second surface of the integrated-circuit chip via a second set of solder joints. The heat spreader includes an adhesion-promotion layer on top of a silicon layer, such that heat generated from the integrated-circuit chip can be efficiently transmitted to and subsequently dissipated by the heat spreader.

Growing community of inventors

Hopewell Junction, NY, United States of America

Leon L Wu