International Business Machines Corporation

Hewlett-packard Company

Globalfoundries Inc.

Leon Jacob Sigal

James Douglas Warnock

David S Wolpert

Eric M Schwarz

Hung Cai Ngo

Robert Michael Bunce

Dieter F Wendel

Tak H Ning

Terence B Hook

K Paul Muller

Philip Joseph Oldiges

Michael H Wood

Ethan Harrison Cannon

Michael S Gray

Aj KleinOsowski

Matthew Thomas Guzowski

Nagashyamala R Dhanwada

Mitchell R DeHond

Ruilong Xie

Sang Hoo Dhong

William Vincent Huott

Hans Mikael Jacobson

Jason D Hibbeler

Phillip John Restle

Paul Gerard Villarrubia

Gregory Gower Freeman

Paul Steven Zuchowski

David E Lackey

Tao Li

Alexander Joel Suess

Arun Joseph

Prabhakar Nandavar Kudva

Tsung-Sheng Kang

Siyuranga O Koswatta

Matthew S Angyal

Kevin W McCullen

Basanth Jagannathan

Robert F Walker

Richard Andre Wachnik

Stephen Larry Runyon

Xin Yuan

Sungjae Lee

Brian A Worth

Patrick M Williams

Charlie Chornglii Hwang

Louis Bernard Bushard

J Campbell Scott

Peter J Camporese

Joel D Lamb

William John Livingstone

Benjamin Neil Trombley

Rani Narayan

Erwin Behnen

Michael R Scheuermann

Timothy A Schell

Arjen Alexander Mets

Amol Anil Joshi

Russell W Mason

Daniel J Poindexter

Ryan Michael Kruse

John E Barwin, Iii

Adam R Jatkowski

Veit Gernhoefer

William W Dungan

Richard Edward Serton

Pieter J Woeltgens

Xiaoyun K Wu

Bharat Biyani

Jason Chung

James Leland

Wendel Dieter

Richard A Wachnick

David Kadzov

A structure including a plurality of nanosheet transistors each comprising a gate. A gate protrusion extends from the gate towards the backside of one of the plurality of electronic devices. A first dielectric liner is located flush against the sidewalls of the gate protrusion. A contact via connected to a backside surface of the gate protrusion. A second dielectric liner located flush again the sidewalls of the contact via.

Backside gate via structure using self-aligned scheme

Method and structures for shared (dual) sources for a single device in semiconductor devices such as very-large-scale integration (VLSI) devices. The shared-source improves or increases a current that passes through the device (e.g., to a drain region associated with the shared-source), which in turn increases a performance of the device. Example improvements may include a delay improvement of the device and associated logic paths and/or a power improvement for the device. The method includes operations for design improvements during a design process by implementing shared-sources in a semiconductor device design.

Cell optimization through source resistance improvement

Method and apparatus for generating an updated power delivery network. Generating the power delivery network includes determining power characteristics for a power delivery network of a circuit design based on logic cells of the circuit design. The power delivery network includes power wires and power staples connecting pairs of the power wires to each other. Further a first one or more of the power staples is remove from the power delivery network based on the power characteristics. Signal wires for the logic cells are routed after removing the first one or more of the power staples. Routing the signal wires includes routing a first signal wire of the signal wires in a routing track corresponding to the first one or more of the power staples.

Generating a power delivery network based on the routing of signal wires within a circuit design

Apparatus for mitigating latch-up within semiconductor devices. A semiconductor device includes a first conductor, a second conductor, and a first gate conductor. The first conductor extends in a first direction, receives a first power supply signal, and is connected to a first electrode. The second conductor extends in the first direction, receives a second power supply signal different from the first power supply signal, and is connected to a second electrode. The first conductor is offset from the second conductor in a second direction perpendicular to the first direction in a top-down view to mitigate formation of parasitic devices within the semiconductor device electrically connecting the first conductor with the second conductor. The first gate conductor is disposed adjacent to the first conductor and the second conductor, is disposed on the first electrode and the second electrode, and receives an input signal.

Semiconductor device design mitigating latch-up

Aspects of the invention include systems and methods configured to provide hierarchical circuit designs that makes use of a color decomposition of library cells having boundary-aware color selection. A non-limiting example computer-implemented method includes placing a plurality of shapes within a hierarchical level of a chip design. The plurality of shapes can include a top boundary shape, a bottom boundary shape, one or more center boundary shapes, and one or more internal shapes. A hierarchical hand-off region is constructed by pinning the top boundary shape to a first mask, pinning the bottom boundary shape to a second mask, and pinning the one or more center boundary shapes to a same mask. The same mask is selected from one of the first mask and the second mask.

Hierarchical color decomposition of library cells with boundary-aware color selection

Embodiments for power generation include defining a power tile within a power distribution network having a grid of power rails, the power tile having logic gates, and applying an initial power grid pattern from a plurality of power grid patterns for the power tile such that initial power grid pattern relates to timing characteristics of the logic gates of the power tile. The power grid patterns each have a different number of connectors connecting one power rail to another power rail in the grid of power rails. A subsequent power grid pattern is selected from the power grid patterns for the power tile such that the subsequent power grid pattern meets a threshold condition for the timing characteristics of the logic gates of the power tile. The timing characteristics for the logic gates are determined based on a voltage drop associated with the subsequent power grid pattern.

Region-based power grid generation through modification of an initial power grid based on timing analysis

Aspects of the invention include a computer-implemented method of chip design. The computer-implemented method of chip design include establishing an architecture with alternating rows of differently colored chip-level shapes. Cells are constrained to be rectangular with restricted widths. Constraint-observing parent and child cells are generated and respectively include boundaries with alternating rows of differently colored cell-level shapes for disposition in the architecture. The parent cell is positioned in the architecture such that the cell-level shapes thereof exhibit row and color alignment with the chip-level shapes. Child cells exhibiting uni-axial or multi-axial reflectivity are instantiated in the parent cell. A color solution is instantiated for each child cell in the parent cell such that cell-level shapes of the child cells exhibit row and color alignment with the cell-level shapes of the parent cell.

Hierarchical color decomposition of process layers with shape and orientation requirements

Aspects of the invention include systems and methods for implementing a CMOS circuit design that uses a sea-of-gates fill methodology to provide latch-up avoidance. A non-limiting example computer-implemented method includes identifying a fill cell in the circuit design. The fill cell can include a power rail, a ground rail, and a field-effect transistor (FET) electrically coupled to the power rail through a via. The method can include disconnecting the via from the power rail and moving the via to a disconnected node in the fill cell. Moving the via decouples a source or drain of the fill cell from a well of the fill cell, preventing latch-up while maintaining via and metal shape density.

Latch-up avoidance for sea-of-gates

Methods, systems and computer program products for providing flexible constraint-based logic cell placement are provided. Aspects include determining a cell placement restriction rule that specifies an offset requirement between a first type of logic cell and a second type of logic cell. Responsive to placing a first cell that is the first type of logic cell within a semiconductor layout, aspects include tagging the first cell with the cell placement restriction rule. Aspects also include placing a second cell that is the second type of logic cell at an initial position within the semiconductor layout. Responsive to determining that the initial position of the second cell violates the cell placement restriction rule, aspects include repositioning the first cell or the second cell to a modified position within the semiconductor layout such that the modified position satisfies the cell placement restriction rule.

Flexible constraint-based logic cell placement

A method and system for improving the performance of a computer in identifying and mitigating electromigration violations of a semiconductor device. A set of library gates is obtained and parasitic layout extraction is performed for each gate in the set of library gates to generate an extracted netlist. One or more passes of an electromigration analysis of the extracted netlist are performed to characterize each gate over a set of input parameters and to generate a maximum slew rate (MAX_SLEW) table and a maximum capacitance (MAX_CAP) table.

Characterizing and simulating library gates to enable identification and elimination of electromigration violations in semiconductor chips

A system and method for enabling the estimation and mitigation of self-heating in chip designs at a much earlier stage in a design flow. The system and method provides unique characterization of each standard cell in a library for its effective thermal resistance based on the topology and layout of the cell, and brings this per standard cell instance based delta-T to be available for the timing closure tools when completing a synthesized design. Thus, at the timing closure process, the generated design is free of self heating violations. The method computes a unique thermal resistance characterization on per standard cell manner&#x2014;based on the topology, function and layout of the standard cell, and uses that to compute the deltaT per instance of the design. This information is presented to a violation mitigation tool which changes the power levels of the cells, logic function to mitigate the self heating violations.

Early analysis and mitigation of self-heating in design flows

An efficient method of calculating maximum current limits for library gates in which a current limit includes the impact of self-heating effects associated with the maximum current. A maximum current solution is obtained in a self-consistent fashion, providing a way of determining the self-consistent solution in a rapid fashion without extensive numerical calculations or simulations. The present method provides a practical approach for characterizing a large library of gates for use in CMOS designs.

Method for an efficient modeling of the impact of device-level self-heating on electromigration limited current specifications

A method of characterizing an electromigration (EM) parameter for use in an integrated circuit (IC) chip design including, inputting a layout of a wire layer and identifying a signal gate-circuit including electrically parallel paths, connected to an output of the signal gate from the layout. Based on widths for each of the paths, determining a maximum possible current for each of the paths, and calculating an average current for each of the paths. Identifying a path that is most limited in its current carrying capacity by possible EM failure mechanisms, and storing in a design library, a possible maximum current output to the identified limiting path, as the EM parameter.

Identifying and mitigating electromigration failures in signal nets of an integrated circuit chip design

A method of generating a power grid to supply current to a plurality of cells of an integrated circuit includes routing an initial power grid representing a power usage estimate for the plurality of cells. The method also includes performing power grid analysis prior to routing of signal wires to make a determination of whether the initial power grid meets power requirements of the integrated circuit, and selectively modifying portions of the initial power grid based on the performing the power grid analysis to generate the power grid.

Power grid generation through modification of an initial power grid based on power grid analysis

A method of determining one or more transistors within a particular circuit to be respectively replaced with a hardened transistor includes: identifying, as not requiring hardening, one or more transistors; identifying, as candidates for hardening, each transistor in the circuit not previously identified as not requiring hardening; and employing the hardened transistor in place of a transistor identified as a candidate for hardening. The circuit is a latch and the transistor is an SOI CMOS FET. The transistor is also an SOI transistor. The series transistor includes first and second series-connected transistors having a shared source/drain region whereby a drain of the first series-connected transistor is merged with a source of the second series-connected transistor.

Apparatus and method for hardening latches in SOI CMOS devices

Growing community of inventors

Monsey, NY, United States of America

Leon Jacob Sigal