Marvell International Limited

Unisys Corporation

Qlogic Corporation

Leon A Krantz

Mark Jeffrey Tadman

Richard Mike Holmes

James A Walch

Kha Nguyen

Michael J North

William W Dennin, Iii

Huy Tu Nguyen

Frank W Campbell

A system including a memory with arrays, a register, and a port. The memory stores an interrupt service routine (ISR). The arrays store respective fields. The port is connected to initiators of a host device and includes a physical layer (PHY) device and a control module. The PHY device: transfers a first frame between the port and a first initiator; and transfers a second frame between the port and the first or a second initiator. The frames include first and second information including respective world wide name addresses and connection rates. The PHY device: compares the first and second information; if there is not a match, interrupts servicing the first frame; and stores an index value for one of the arrays in the register. The control module, based on the index value, executes the ISR to service the second frame based on the fields in the one of the arrays.

Method and apparatus for transferring frames with different world wide name addresses and connection rates between initiators of a host device and a port

A method and system for transferring frames from a storage device to a host system via a controller is provided. The method includes transferring frames from a transport module to a link module; and sending an acknowledgment to the transport module, wherein the link module sends the acknowledgement to the transport module and it appears to the transport module as if the host system sent the acknowledgement. The frames in the controller are tracked by creating a status entry indicating that a new frame is being created; accumulating data flow information, while a connection to transfer the frame is being established by a link module; and updating frame status as frame build is completed, transferred, and acknowledged. The controller includes, a header array in a transport module of the controller, wherein the header array includes plural layers and one of the layers is selected to process a frame.

System and method for transmitting data in storage controllers

A serial attached small computer systems interface (SAS) module includes a first port with (i) a first physical layer device and (ii) a first port control module. The first physical layer device communicates with a plurality of initiators. The first port control module comprises a first world wide number (WWN) table. The first WWN table comprises connection rates of the plurality of initiators during communication with the first physical layer device. Each of the connection rates is a last connection rate of a respective one of the plurality of initiators.

WWN table management systems and methods

A controller including an interface module and an index module. The interface module is configured to connect devices. The index module is configured to include, in a table stored in memory, an entry for each of the devices. Each entry includes an address field. The index module is configured to: receive a frame of data including an address of one of the devices; compare the address to the address fields associated with the entries in the table; in response to the address matching one of the address fields, access an index value identifying an entry of the table when the address matches one of the address fields; and in response to the address not matching one of the address fields, generate the index value. The index value is used to connect the device associated with the matching one of the address fields with the one of the devices.

Storage controllers with dynamic WWN storage modules and methods for managing data and connections between a host and a storage device

A method and system for transferring data between a host and a Serial Attached Small Computer Interface ('SAS') device using a storage controller is provided. The storage controller includes, a World Wide Name ('WWN') module that includes a table having plural entries, wherein each row includes a WWN address, an initiator tag value field, an input/output counter value that tracks plural commands for a connection. A WWN index value represents the address of a row having plural entries. The method includes, comparing frame elements of incoming frames, including a unique WWN address with the WWN module entries; and if there is a match, updating a counter value for a connection between the storage controller and a device sending frames. The counter value is increased when a command frame is received and decreased when a command is executed and a response is sent to the device.

A data storage controller includes a link module that selectively sets an interrupt. A control module is external to the link module that includes N buffers where N is an integer greater than 0. The controller allocates at least one of the N buffers to store world wide name ('WWN') table data in response to the interrupt. The controller also internally manages the WWN table data.

WWN table management system and method

A method and system for arbitrating access to a shared disk controller resource, including a buffer memory of a hard disk controller (HDC). An access cycle with a first cycle duration are disclosed and a first amount of time is allocated to a first accessing unit including an error correction code (ECC) engine, a microprocessor first-in-first-out (FIFO) unit, or a memory refresh/data format data fetch unit. The shared controller resource is accessed using the first accessing unit for a first duration, where the first duration is no greater than the first amount of time. A second amount of time and an unused portion of the first amount of time is allocated to a second accessing unit such as a disk formatter. Arbitration limit registers may be used to specify the number of HDC clock cycles per access cycle available to an accessing unit during which it can access the buffer memory. A global arbitration limit counter may be used to keep track of the duration of the accessing units.

Methods and systems for arbitrating access to a disk controller buffer memory by allocating various amounts of times to different accessing units

A system whereby a receiving module, in a mixed network of hardware and software-emulated modules, requires an Interrupt before it can use a Get Message OP to access a message from a message queue and which also provides a Fast Empty of messages in a message queue by eliminating the need for an Interrupt before each succeeding message access.

Interrupt handling system for message transfers in network having mixed

A method for message transfers between digital modules in a network where some modules are hardware implemented and some modules are emulated in software. An Auxiliary Message Arbitrator Unit utilizes Main Memory storage for messages destined for receiving modules. Algorithmic sequencing means maintains chronological transfer operations of messages and uses hard and soft Interrupt signal queues to inform respective hard and soft modules of pending messages for them to retrieve.

Control method for message communication in network supporting software

A method and system of message transfers in a multiple sender-multiple receiver network provides a specialized sequence for a Sender to acquire a message slot and place a message in a message queue, and a retrieval sequence for the Receiving module that insures message transmission integrity and proper chronological sequence of message delivery.

Message transfer system and control method for multiple sending and

A hardware message transfer control unit designated as the Auxiliary Message Arbitrator Unit (AMA) manages message transfers and transfer protocols in a network of sending and receiving digital hardware modules. Flexibility of network expansion to include software emulated digital modules to the hardware modules is provided in RAM circuitry at the message transfer control unit.

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Mission Viejo, CA, United States of America

Leon A Krantz